參數(shù)資料
型號: MPR121QR2
廠商: Freescale Semiconductor
文件頁數(shù): 10/27頁
文件大?。?/td> 0K
描述: IC CTLR TOUCH SENSOR 20-QFN
產(chǎn)品培訓(xùn)模塊: MPR121: Low-Power Touch Sensor
產(chǎn)品目錄繪圖: MPR121QR2CT
特色產(chǎn)品: MPR121 Proximity Capacitive Touch Sensor Controller
標(biāo)準(zhǔn)包裝: 1
類型: 電容式,近程傳感器
輸入數(shù)/鍵: 12
評估套件: 可供
數(shù)據(jù)接口: I²C,串行
電源電壓: 1.71 V ~ 3.6 V
電流 - 電源: 29µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-UFQFN
供應(yīng)商設(shè)備封裝: 20-QFN(3x3)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 2808 (CN2011-ZH PDF)
其它名稱: MPR121QR2DKR
MPR121
Sensors
18
Freescale Semiconductor, Inc.
SCTS: Skip Charge Time Search.
1: Skip CDTx search and update when autoconfiguration or autoreconfiguration, and current global CDT or CDTx are used
for respective channels. CDT or CDTx needs to be specified by the designer manually before operation. Setting the SCTS
to “1” results in a shorter time to complete autoconfiguration. This is useful for when the designer has obtained the correct
CDTx / CDT, and is confident that the current CDT and CDTx settings work in all conditions.
0: Both CDTx and CDCx will be searched and set by autoconfiguration and/or autoreconfiguration.
ACFIE: Auto-configuration fail interrupt enable. 1: Enable, 0: Disable
ARFIE: Auto-reconfiguration fail interrupt enable. 1: Enable, 0: Disable
OORIE: Out-of-range interrupt enable. 1: Enable, 0: Disable
USL: Up-Side Limit. This value sets the electrode data level up limit for the boundary check in autoconfiguration and
autoreconfiguration operation.
LSL: Low-Side Limit. This value sets the electrode data level low limit for the boundary check in autoconfiguration and
autoreconfiguration operation.
TL: Target Level. This value is the expected target electrode data level for autoconfiguration and autoreconfiguration, that is, after
successful autoconfiguration and autoreconfiguration, the measured electrode data level when untouched shall be close to the
TL value. TL shall be in between of USL and LSL.
The three parameters, USL, LSL and TL, are in the format similar to the baseline value; only the eight high bits are accessible
by user and the two low bits are set to zero automatically. The USL/LSL/TL data needs to be shifted left two bits before comparing
with the electrode data or the 10-bit baseline value.
In order to have a valid auto-configuration result, USL/LSL/TL values should follow the relation that 255 > USL > TL > LSL > 0.
For example, USL = 200, TL = USL*0.9 = 180, LSL = USL*0.5 = 100.
It is possible that in a end user environment, the channel differences may be significant. This is because the same set of USL/
LS/TL data is being used for all channels. It is important that the parameters not be set too close together. This makes it difficult
for the autoconfiguration to find a suitable charge setting for a specific channel. In this case, the electrode data might easily go
out of USL and LSL setting limits. Since the data is out-of-range, the channel status becomes OOR. If the channel is still OOR
after the autoconfiguration has been run, it may indicate that the settings for this channel have not yet been optimized. One
solution to this problem is to manually review the USL/LSL/TL settings. Another possible reason why the channel status could
be OOR is a problem with the channel itself. This could be caused by a short to ground, short to the power rail, or short to the
pad of the other channel.
For the TL setting, a good practice is to try to set it close to the USL. This so the charge field can be set to detect a weak touch.
On the other hand, the TL should not be set too close to the USL so that it is constantly exceeding the limit. For example, the
electrode data from the end user’s environment might have a much wider variance of readings. Some of the readings might
exceed the USL, causing the auto-configuration to fail. For this reason, if the amount of capacitance change in the end user
environment is significant, it is suggested that the USL and TL be set low enough to give some headroom for possible capacitance
variations.
Up-Side Limit Register (0x7D)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Read
USL
Write
Low-Side Limit Register (0x7E)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Read
LSL
Write
Target Level Register (0x7F)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Read
TL
Write
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