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參數(shù)資料
| 型號(hào)： | MPM22CGC600A |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 600 MHz, MICROPROCESSOR, XMA |
| 封裝： | MMC-2 |
| 文件頁(yè)數(shù)： | 15/68頁(yè) |
| 文件大?。?/td> | 966K |
| 代理商： | MPM22CGC600A |
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Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep Technology
16
Datasheet
243356-006
3.1.10
ITP and JTAG Pins
Table 10 provides descriptions of the ITP and JTAG signals, which the system manufacturer can
use to implement a JTAG chain and an ITP port if desired.
NOTE: FS_RESET# and FS_PRDY# are pulled up to VTT inside the mobile processor core.
3.1.11
Miscellaneous Pins
Table 11 provides descriptions of the miscellaneous signal pins.
Table 10. ITP and JTAG Pins
Name
Type
Voltage
Description
TDO
O D
V_CPUPU
JTAG Test Data Out: A serial output port. TAP instructions and data
are shifted out of the processor from this port.
TDI
I
VTT
JTAG Test Data In: A serial input port. TAP instructions and data are
shifted into the processor from this port.
TMS
I
VTT
JTAG Test Mode Select: This pin controls the TAP controller change
sequence.
TCLK
I
VTT
JTAG Test Clock: A testability clock for clocking the JTAG boundary
scan sequence.
TRST#
I
VTT
JTAG Test Reset: This signal asynchronously resets the TAP
controller in the processor.
FS_PREQ#
I
VTT
Debug Mode Request: This signal is driven by the ITP and makes a
request to enter debug mode.
FS_PRDY#
O
VTT
Debug Mode Ready: This signal is driven by the processor and
informs the ITP that the processor is in debug mode.
FS_RESET#
O
VTT
Processor Reset: The processor reset status to the ITP.
VTT
O
VTT
GTL+ Termination Voltage: This pin is used by the POWERON pin
on the ITP debug port to determine when the target system is on. The
POWERON pin is pulled up using a 1-K
resistor to VTT. Other ITP
signals might use this power rail for pullup.
Table 11. Miscellaneous Pin Descriptions
Name
Type
Number
Description
Module ID[3:0]
O
CMOS
4
Module Revision ID: These pins track the revision level of the mobile
module. A 100-K pullup resistor to V_3S must be placed on the system
electronics for these signals. See Section 8.0 for more detail.
Ground
I
45
Ground
Reserved
RSVD
33
Unallocated Reserved pins.
All Reserved pins must not be connected.
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