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| 型號： | MPM21CUB600A |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 600 MHz, MICROPROCESSOR, XMA |
| 封裝： | MMC-2 |
| 文件頁數(shù)： | 29/64頁 |
| 文件大?。?/td> | 826K |
| 代理商： | MPM21CUB600A |
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Celeron
Processor Mobile Module MMC-2
at 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
243357-005
Datasheet
29
Table 20 describes the signal quality specifications at the processor core for the PSB clock (BCLK)
signal. Figure 4 describes the signal quality waveforms for the PSB clock at the processor core pins
For proper signal termination, refer to the “Clocking Guidelines” section in the Mobile Pentium
III Processor/440BX AGPset Recommended Design and Debug Practices (RDDP-A) 100 MHz Rev.
2.0 (SC-2760).
NOTES:
1. On the rising edge of BCLK, there must be a minimum overshoot to 2.0V. The clock must rise monotonically
between VIL,BCLK and 2.0V and fall monotonically between VIH,BCLK and VIL,BCLK.
2. These specifications apply only when BCLK is running. See Table 18 for the DC specifications when BCLK is
stopped. BCLK may not be above VIH,BCLK,MAX or below VIL,BCLK,MIN for more than 50% of the clock cycle.
3. The rising edge ringback voltage is the minimum absolute voltage that the BCLK signal can dip back to after
passing the VIH,BCLK,MIN (rising) voltage limits. The falling edge ringback voltage is the maximum absolute
voltage that the BCLK signal can dip back to after passing the VIL,BCLK,MAX (falling) voltage limits.
4. Specifications labeled N/A are not available.
Figure 4. BCLK Waveform at the Processor Core Pins
Table 20. BCLK Signal Quality AC Specifications at the Processor Core
T#
Parameter
Min
Max
Unit
Notes
V1
VIL,BCLK
-0.3
0.7
V
Note 1
V2
VIH,BCLK
1.7
2.625
V
Note 1
V3
VIN Absolute Voltage Range
-0.7
3.5
V
Undershoot, Overshoot, Note 2
V4
Rising Edge Ringback
1.7
N/A
V
Absolute Value, Notes 3, 4
V5
Falling Edge Ringback
N/A
0.7
V
Absolute Value, Notes 3, 4
BCLK Rising/Falling Slew Rate
0.8
4.0
V/nS
V1MAX
V3MAX
V2MIN
V4
V3MIN
V5
V0012-00
T3
T6
T4
T5
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