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參數(shù)資料
| 型號： | MPE603EFE100TX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | 32 X 32 MM, 0.50 MM PITCH, WIRE BOND, CERAMIC, QFP-240 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 250K |
| 代理商： | MPE603EFE100TX |
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PID6-603e Hardware Specifications, Rev 2
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 603e.
1.8.1 PLL Conguration
The 603e PLL is congured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the PLL
conguration signals set the internal CPU and VCO frequency of operation. The PLL conguration for the
603e is shown in Table 12 for nominal frequencies.
Table 12. PowerPC 603e Microprocessor PLL Configuration
PLL_CFG[0–3]
CPU Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core -to-
VCO
Multiplier
Bus
16.67
MHz
Bus
20
MHz
Bus
25
MHz
Bus
33.33
MHz
Bus
40
MHz
Bus
50
MHz
Bus
60
MHz
Bus
66.67
MHz
0000
1x
2x
—————
50
(100)
60
(120)
66.67
(133)
0001
1x
4x
—————
50
(200)
60
(240)
66.67
(266)
1100
1.5x
2x
50
(100)
60
(120)
75
(150)
90
(180)
100
(200)
0100
2x
—
66.67
(133)
80
(160)
100
(200)
120
(240)
133.33
(266)
0101
2x
4x
—
50
(200)
66.67
(266)
————
0110
2.5x
2x
—
50
(100)
62.5
(125)
83.33
(166)
100
(200)
125
(250)
——
1000
3x
2x
50
(100)
60
(120)
75
(150)
100
(200)
120
(240)
———
1110
3.5x
2x
58.4
(117)
70
(140)
87.5
(175)
116.67
(233)
————
1010
4x
2x
66.67
(133)
80
(160)
100
(200)
133.33
(266)
————
0011
PLL bypass
1111
Clock off
Notes:
1. PLL_CFG[0–3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL congurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the 603e; see Section 1.4.2.1, “Clock
AC Specications,” for valid SYSCLK and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specications given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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