參數(shù)資料
型號(hào): MPD78C12AGFA-XXX-3BE
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 15 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-64
文件頁(yè)數(shù): 3/62頁(yè)
文件大?。?/td> 617K
代理商: MPD78C12AGFA-XXX-3BE
PD78C10A(A), 78C11A(A), 78C12A(A)
9
Pin name
MODE0
MODE1
(Mode)
NMI
(Non-Maskable
Interrupt)
INT1
(Interrupt
Request)
AN7-0
(Analog Input)
VAREF
(Reference
Voltage)
AVDD
(Analog VDD)
AVSS
(Analog VSS)
X1, X2
(Crystal)
RESET
(Reset)
STOP
(Stop)
VDD
VSS
I/O
I
Function
In the
PD78C11A(A) and 78C12A(A), the MODE0 pin is set to “0” (low) and the MODE1
pin is set to “1” (high)(Note).
In the
PD78C10A(A), the MODE0 and MODE1 pins are used to select one of three external
memory sizes: 4 Kbytes, 16 Kbytes, or 64 Kbytes.
If MODE0 and MODE1 are both set to “1”(Note), a control signal is output synchronously
with ALE.
This is a falling edge-triggered nonmaskable interrupt input pin.
INT1 is a rising edge-triggered maskable interrupt input pin. It is also an AC-input, zero-
cross detection pin.
These are eight analog inputs to the A/D converter. AN4 to AN7 can also be used as inputs
for falling edge detection.
This pin can be used as a reference voltage input for the A/D converter or as a control
pin for A/D converter operation.
This is the power supply pin for the A/D converter.
This is the ground pin for the A/D converter.
These are the crystal pins for the system clock oscillator. X1 inputs an external clock.
X2 inputs the inverted clock from X1.
This is the system reset input pin (active low).
This is the control signal input pin during hardware STOP mode. Low-level input stops
the system clock oscillator.
Positive power supply pin
Ground pin
MODE0
MODE1
External memory
0
4 Kbytes
1
0
16 Kbytes
1
64 Kbytes
Note
These must be pulled up using a pull-up resistance value (R) of 4 (k
) ≤ R ≤ 0.4 tCYC (k). (tCYC is in
ns units.)
Remark
On-chip pull-up resistors for Ports A, B, and C are available as mask options on the
PD78C11A(A)
or 78C12A(A).
5
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