參數(shù)資料
型號(hào): mPD789326GB-xxx-8ET
廠商: NEC Corp.
元件分類(lèi): 8位微控制器
英文描述: 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述: 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁(yè)數(shù): 54/96頁(yè)
文件大小: 482K
代理商: MPD789326GB-XXX-8ET
Preliminary Product Information U14673EJ1V0PM00
54
μ
PD789322,789324,789326,789327
(2) LCD clock control register (LCDC0)
This register is used to set the internal and LCD clocks. The frame frequency is determined by the number of
LCD clock time divisions.
LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-27. Format of LCD Clock Control Register 0
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
LCDC0
0
0
0
0
LCDC03
LCDC02
LCDC01
LCDC00
FFB2H
00H
R/W
LCDC03
LCDC02
Internal clock (f
CLK
) selection
Note
0
0
f
XT
(32.768 kHz)
0
1
f
X
/2
5
(156.3 kHz)
1
0
f
X
/2
6
(78.1 kHz)
1
1
f
X
/2
7
(39.1 kHz)
LCDC01
LCDC00
LCD clock (f
LCD
) selection
0
0
f
CLK
/2
6
0
1
f
CLK
/2
7
1
0
f
CLK
/2
8
1
1
f
CLK
/2
9
Note
Select f
X
so that a clock of at least 32 kHz is set for the internal clock f
CLK
.
Remarks 1.
f
X
: Main system clock oscillation frequency
2.
f
XT
: Subsystem clock oscillation frequency
3.
The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz
Caution
Always set bits 4 to 7 to 0.
Examples of the frame frequencies when the internal clock is f
XT
(32.768 kHz) are shown in Table 5-14 below.
Table 5-14. Frame Frequency (Hz)
LCD Clock (f
LCD
)
Time Division
f
XT
/2
(64 Hz)
9
f
XT
/2
(128 Hz)
8
f
XT
/2
(256 Hz)
7
f
XT
/2
(512 Hz)
6
4
16
32
64
128
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