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參數(shù)資料
| 型號(hào)： | MPD703224GC(A)-8EU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, LQFP-100 |
| 文件頁數(shù)： | 27/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MPD703224GC(A)-8EU |
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DATA SHEET U15870EE1V1DS00
PD703223, PD703224, PD703225, PD703226
2.5.7 A/D converter
TA = -40°C to +85°C, VDD50 = VDD51 = AVDD = 4.5 V ~ 5.5 V, VSS51 = VSS30 = VSS31 = AVSS = 0 V
Notes: 1. The quantization error is not included
2. The conversion time TCONV depends on the setting of the ADM register
3. The sampling time TSAM depends on the setting of the ADM register
4. The leakage current specification becomes valid if the A/D converter reference voltage is
switched off.
2.5.8 Voltage regulator
TA = -40°C to +85°C, VDD50 = VDD51 = AVDD = 4.0 V ~ 5.5 V, VSS51 = VSS30 = VSS31 = AVSS = 0 V
Note: CREGC0 & CREGC1 are respectively connected to REGC0 and REGC1 pins. They must have the
same value.
Remark:
To improve EMI and noise filtering, it might be necessary to connect small size capaci-
tances in parallel with CREGC0 & CREGC1.
Table 2-19:
A/D Converter Characteristics
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Resolution
-
10
Bit
Overall ErrorNote 1
-
±3LSB
Conversion timeNote 2
TCONV
512
s
Sampling timeNote 3
TSAM
TCONV/6
s
Analog input voltage
VIAN
AVSS
AVDD
V
Analog supply current
IAVDD
A/D converter is operating
4.0
8.0
mA
ILAVDD A/D converter is stoppedNote 4
1.0
5.0
A
Table 2-20:
Voltage regulator
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Output voltage
stabilization time
tREG
Time starts when VDD50 reaches
minimum value of 4.0 V
(CREGC0 = CREGC1 = 1 F)
Note
2ms
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