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參數(shù)資料
| 型號(hào)： | MPC9952FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 96K |
| 代理商： | MPC9952FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC9952/D
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
282
Low Voltage PLL Clock Driver
The MPC9952 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree applications. The device fea-
tures a fully integrated PLL with no external components required. With
output frequencies of up to 180MHz and eleven low skew outputs the
MPC9952 is well suited for high performance designs. The device em-
ploys a fully differential PLL design to optimize jitter and noise rejection
performance. Jitter is an increasingly important parameter as more micro-
processors and ASiC’s are employing on chip PLL clock distribution.
Fully Integrated PLL
Output Frequency up to 180MHz
High Impedance Disabled Outputs
Compatible with PowerPC, Intel and High Performance RISC Micro-
processors
Output Frequency Configurable
LQFP Packaging
±100ps Cycle–to–Cycle Jitter
The MPC9952 features three banks of individually configurable out-
puts. The banks contain 5 outputs, 4 outputs and 2 outputs. The internal
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1.
The output frequency relationship is controlled by the fsel frequency con-
trol pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL
compatible inputs.
The MPC9952 uses external feedback to the PLL. This features allows
for the use of the device as a “zero delay” buffer. Any of the
eleven outputs can be used as the feedback to the PLL. The VCO_Sel
pin allows for the choice of two VCO ranges to optimize PLL stability and
jitter performance. The MR/OE pin allows the user to force the outputs
into high impedance for board level test.
For system debug the PLL of the MPC9952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the
design for debug purposes.
The outputs of the MPC9952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.
For applications using series terminated transmission lines each MPC9952 output can drive two lines. This capability provides an
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines
consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
Rev 2
2
MPC9952
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
See Upgrade Product – MPC9352
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9952FA | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9993ACR2 | 9993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9993AC | 9993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MSFLDL-TTL-200 | ACTIVE DELAY LINE, TRUE OUTPUT, SIP4 |
| MSFLDL-TTL-19 | ACTIVE DELAY LINE, TRUE OUTPUT, SIP4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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