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參數(shù)資料
| 型號： | MPC9865VM |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PBGA100 |
| 封裝： | 11 X 11 MM, 1 MM PITCH, LEAD FREE, MO-192DAC-1, MAPBGA-100 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MPC9865VM |
Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC9865
Figure 4. MPC9865 AC Test Reference (LVCMOS Outputs)
Table 9. AC Characteristics (VDD = 3.3 V ± 5%, VDDOAB = 3.3 V ± 5%, TA= –40°C to +85°C)
(1) (2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50
Ω to V
TT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Input and Output Timing Specification
fref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode(3)
3. In bypass mode, the MPC9865 divides the input reference clock.
25
33
25
250
MHz
PLL bypass
fVCO
VCO Frequency Range
2000
MHz
fMCX
Output Frequency
Bank A output
Bank B output
15.87
200
MHz
PLL locked
frefPW
Reference Input Pulse Width
2
ns
frefCcc
Input Frequency Accuracy
100
ppm
tr, tf
Output Rise/Fall Time
150
500
ps
20% to 80%
DC
Output Duty Cycle
45
50
55
%
Bank A and B
PLL Specifications
tLOCK
Maximum PLL Lock Time
10
ms
treset_ref
MR Hold Time on Power Up
10
ns
treset_pulse
MR Hold Time
10
ns
Skew and Jitter Specifications
tsk(O)
Output-to-Output Skew (within a bank)
50
ps
tsk(O)
Output-to-Output Skew (across banks A and B)
100
ps
VDDOA = 3.3 V
VDDOB = 3.3 V
tJIT(CC)
Cycle-to-Cycle Jitter
150
ps
Bank A and B
tJIT(PER)
Period Jitter
150
ps
Bank A and B
tr, tf
Output Rise/Fall Time
TBD
ns
20% to 80%
Pulse
Generator
Z = 50
Ω
RT = 50Ω
ZO = 50Ω
DUT MPC9865
VTT
ZO = 50Ω
RT = 50Ω
VTT
MPC9865
Clock Generator for PowerQUICC III
NETCOM
IDT Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9865
8
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