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參數(shù)資料
| 型號： | MPC9653FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 159K |
| 代理商： | MPC9653FA |
MPC9653
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
525
APPLICATIONS INFORMATION
Programming the MPC9653
The MPC9653 supports output clock frequencies from 25 to
125 MHz. Two different feedback divider configurations can be
used to achieve the desired frequency operation range. The
feedback divider (VCO_SEL) should be used to situate the
VCO in the frequency lock range between 200 and 500 MHz for
stable and optimal operation. Two operating frequency ranges
are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table
illustrates the configurations supported by the MPC9653. PLL
zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the
input frequency is within the specified PLL reference frequency
range.
Power Supply Filtering
The MPC9653 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA_PLL power supply impacts the device characteristics,
for instance I/O jitter. The MPC9653 provides separate power
supplies for the output buffers (VCC) and the phase-locked loop
(VCCA_PLL) of the device. The purpose of this design technique
is to isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
illustrates a typical power supply filter scheme. The MPC9653
frequency and phase stability is most susceptible to noise with
spectral content in the 100 kHz to 20 MHz range. Therefore the
filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is the DC
voltage drop across the series filter resistor RF. From the data
sheet the ICCA current (the current sourced through the VCC_PLL
pin) is typically 5 mA (10 mA maximum), assuming that a
minimum of 2.985 V must be maintained on the VCC_PLL pin.
Figure 3. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in Figure 3, the filter cut-off frequency is around 4 kHz
and the noise attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9653 has several
design features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
Using the MPC9653 in Zero-Delay Applications
Nested clock trees are typical applications for the MPC9653.
Designs using the MPC9653 as LVCMOS PLL fanout buffer
with zero insertion delay will show significantly lower clock skew
than clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC9653 clock driver
allows for its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference edge
resulting a near zero delay through the device (the propagation
delay through the device is virtually eliminated). The maximum
insertion delay of the device in zero-delay applications is
measured between the reference clock input and any output.
This effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Table 7. MPC9653 Configurations (QFB connected to FB_IN)
BYPASS
PLL_EN
VCO_SEL
Operation
Frequency
Ratio
Output range (fQ0–7)
VCO
0
X
Test mode: PLL and divider bypass
fQ0–7 = fREF
0–200 MHz
n/a
1
0
Test mode: PLL bypass
fQ0–7 = fREF ÷ 4
0–50 MHz
n/a
1
0
1
Test mode: PLL bypass
fQ0–7 = fREF ÷ 8
0–25 MHz
n/a
1
0
PLL mode (high frequency range)
fQ0–7 = fREF
50 to 125 MHz
fVCO = fREF 4
1
PLL mode (low frequency range)
fQ0–7 = fREF
25 to 62.5 MHz
fVCO = fREF 8
VCC_PLL
VCC
MPC9653
10 nF
RF = 5–15
CF= 22 F
CF
33...100 nF
RF
VCC
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