參數(shù)資料
型號(hào): MPC962309D-1H
廠商: MOTOROLA INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 97-3102A24-5P
中文描述: PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁(yè)數(shù): 4/12頁(yè)
文件大?。?/td> 447K
代理商: MPC962309D-1H
MPC962305 MPC962309
TIMING SOLUTIONS
MOTOROLA
Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices
1
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t
1
Output Frequency
30-pF load
10-pF load
10
10
100
133.33
MHz
MHz
Duty Cycle
2
= t
2
÷
t
1
Measured at 1.4 V, F
OUT
= 66.67 MHz
40.0
50.0
60.0
%
t
3
Rise Time
2
Measured between 0.8 V and 2.0 V
2.50
ns
t
4
Fall Time
2
Measured between 0.8 V and 2.0 V
2.50
ns
t
5
Output to Output Skew
2
All outputs equally loaded
250
ps
t
6A
Delay, REF Rising Edge to
CLKOUT Rising Edge
2
Measured at V
DD
/2
0
±
350
ps
t
6B
Delay, REF Rising Edge to
CLKOUT Rising Edge
2
Measured at V
DD
/2. Measured in PLL Bypass Mode,
MPC962309 device only
1
5
8.7
ns
t
7
Device to Device Skew
2
Measured at V
DD
/2 on the CLKOUT pins of devices
0
700
ps
t
J
Cycle to Cycle Jitter
2
Measured at 66.67 MHz, loaded outputs
200
ps
t
LOCK
PLL Lock Time
2
Stable power supply, valid clock presented on REF pin
1.0
ms
Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices
1
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t
1
Output Frequency
30-pF load
10-pF load
10
10
100
133.33
MHz
MHz
Duty Cycle
2
= t2
÷
t1
Measured at 1.4 V, F
OUT
= 66.67 MHz
40.0
50.0
60.0
%
Duty Cycle
2
= t2
÷
t1
Measured at 1.4 V, F
OUT
< 50 MHz
45.0
55.0
55.0
%
t
3
Rise Time
2
Measured between 0.8 V and 2.0 V
1.50
ns
t
4
Fall Time
2
Measured between 0.8 V and 2.0 V
1.50
ns
t
5
Output to Output Skew
2
All outputs equally loaded
250
ps
t
6A
Delay, REF Rising Edge to
CLKOUT Rising Edge
2
Measured at V
DD
/2
0
±
350
ps
t
6B
Delay, REF Rising Edge to
CLKOUT Rising Edge
2
Measured at V
DD
/2. Measured in PLL Bypass Mode,
MPC962309 device only
1
5
8.7
ns
t
7
Device to Device Skew
2
Measured at V
DD
/2 on the CLKOUT pins of devices
0
700
ps
t
8
Output Slew Rate
2
Measured between 0.8 V and 2.0 V using Test Circuit #2
1
V/ns
t
J
Cycle to Cycle Jitter
2
Measured at 66.67 MHz, loaded outputs
200
ps
t
LOCK
PLL Lock Time
2
Stable power supply, valid clock presented on REF pin
1.0
ms
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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