參數(shù)資料
型號： MPC9600FAR2
廠商： MOTOROLA INC
元件分類： 時鐘及定時
英文描述： PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： PLASTIC, LQFP-48
文件頁數(shù)： 8/12頁
文件大?。?/td> 180K
代理商： MPC9600FAR2
MPC9600
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
178
Table 4: DC CHARACTERISTICS (VCC = 2.5 V ±5%, TA = –40° to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.7
V
LVCMOS
VPP
Peak-to-peak input voltage (DC)
PCLK, PCLK
250
mV
LVPECL
VCMRa
Common Mode Range (DC)
PCLK, PCLK
1.0
VCC-0.6
V
LVPECL
VOH
Output High Voltage
1.8
V
IOH=-15 mAb
VOL
Output Low Voltage
0.6
V
IOL= 15 mA
ZOUT
Output Impedance
17 – 20
W
IIN
Input Leakage Current
±150
A
VIN = VCC or GND
ICCA
Maximum PLL Supply Current
3.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. The MPC9600 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated trans-
mission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output.
Table 5: AC CHARACTERISTICS (VCC = 3.3 V ±5% or VCC = 2.5 V ±5%, TA = –40° to +85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
B8 feedback (FSEL_FB=0)
B12 feedback (FSEL_FB=1)
Static test mode (VCCA = GND)
25
16.67
0
50
33
500
MHz
PLL locked
VCCA = GND
fVCO
VCO Frequency
200
400
MHz
fMAX
Maximum Output Frequency
B2 outputs (FSELx=0)
B4 outputs (FSELx=1)
100
50
200
100
MHz
PLL locked
frefDC
Reference Input Duty Cycle
25
75
%
VPP
Peak-to-peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
VCMRb
Common Mode Range
PCLK, PCLK (VCC = 3.3 V
±5%)
PCLK, PCLK (VCC = 2.5 V
±5%)
1.2
VCC-0.8
VCC-0.6
V
LVPECL
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
see Figure 12
t()
Propagation Delay (static phase offset)
CCLK to FB_IN
PECL_CLK to FB_IN
–60
+30
+40
+130
+140
+230
ps
PLL locked
tsk(o)
Output-to-output Skew
all outputs, single frequency
all outputs, multiple frequency
within QAx output bank
within QBx outputs
within QCx outputs
70
30
40
30
150
75
125
75
ps
Measured at
coincident
rising edge
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
see Figure 12
tPLZ, HZ
Output Disable Time
10
ns
tPZL, ZH
Output Enable Time
10
ns
BW
PLL Closed Loop Bandwidth
B8 feedback (FSEL_FB=0)
B12 feedback (FSEL_FB=1)
1.0 – 10
0.6 – 4.0
MHz
–3 dB point of
PLL transfer
characteristic
2
相關(guān)PDF資料
PDF描述
MPC9600FA PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
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MPC9608FAR2 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC9608 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1:10 LVCMOS Zero Delay Clock Buffer
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MPC9608ACR2 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
MPC9608FA 功能描述:時鐘緩沖器 3.3V 200MHz Clock Generator RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
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