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參數(shù)資料
| 型號(hào)： | MPC9600FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大小： | 180K |
| 代理商： | MPC9600FAR2 |
MPC9600
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
182
Using the MPC9600 in zero–delay applications
Nested clock trees are typical applications for the
MPC9600. For these applications the MPC9600 offers a differ-
ential LVPECL clock input pair as a PLL reference. This allows
for the use of differential LVPECL primary clock distribution
devices such as the Motorola MC100ES6111 or
MC100ES6226, taking advantage of its superior low-skew per-
formance. Clock trees using LVPECL for clock distribution and
the MPC9600 as LVCMOS PLL fanout buffer with zero inser-
tion delay will show significantly lower clock skew than clock
distributions developed from CMOS fanout buffers.
The external feedback option of the MPC9600 PLL allows
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the MPC9600
in zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset (SPO or t()), I/O jitter (tJIT(), phase or
long-term jitter), feedback path delay and the output-to-output
skew (tSK(O) relative to the feedback output.
Calculation of part-to-part skew
The MPC9600 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (CCLK or PCLK)
of two or more MPC9600 are connected together, the maxi-
mum overall timing uncertainty from the common CCLK input
to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 6. MPC9600 max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (
± 3s) is assumed, resulting in a worst
case timing uncertainty from input to any output of -261 ps to
341 ps relative to CCLK (VCC=3.3V and fVCO = 200 MHz):
tSK(PP) =
[–60ps...140ps] + [–150ps...150ps] +
[(17ps
@ –3)...(17ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–261ps...341ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number shown
in the AC characteristic table for VCC=3.3V (17 ps RMS). I/O
jitter is frequency dependant with a maximum at the lowest
VCO frequency (200 MHz for the MPC9600). Applications us-
ing a higher VCO frequency exhibit less I/O jitter than the AC
characteristic limit. The I/O jitter characteristics in Figure 7 can
be used to derive a smaller I/O jitter number at the specific
VCO frequency, resulting in tighter timing limits in zero-delay
mode and for part-to-part skew tSK(PP).
Figure 7. Max. I/O Jitter versus VCO frequency for
VCC=2.5V and VCC=3.3V
Driving Transmission Lines
The MPC9600 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20
the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the meth-
od of choice. In a point-to-point scheme either series termi-
nated or parallel terminated transmission lines can be used.
The parallel technique terminates the signal at the end of the
line with a 50
resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MPC9608 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1:10 LVCMOS Zero Delay Clock Buffer |
| MPC9608AC | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9608ACR2 | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9608FA | 功能描述:時(shí)鐘緩沖器 3.3V 200MHz Clock Generator RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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