參數(shù)資料
型號: MPC9448ACR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 時鐘及定時
英文描述: 9448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: PLASTIC, LQFP-32
文件頁數(shù): 8/10頁
文件大小: 395K
代理商: MPC9448ACR2
6
MPC9448
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
587
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the situa-
tion in Figure 6 “Optimized Dual Line Termination” should be
used. In this case, the series terminating resistors are reduced
such that when the parallel combination is added to the output
buffer impedance the line impedance is perfectly matched.
Figure 6. Optimized Dual Line Termination
17
MPC9448
OUTPUT
BUFFER
RS = 16
ZO = 50
RS = 16
ZO = 50
17
+ 16 k 16 = 50 k 50
25
= 25
Power Consumption of the MPC9448 and Thermal Man-
agement
The MPC9448 AC specification is guaranteed for the entire
operating frequency range up to 350 MHz. The MPC9448
power consumption and the associated long-term reliability
may decrease the maximum frequency limit, depending on op-
erating conditions such as clock frequency, supply voltage,
output loading, ambient temperture, vertical convection and
thermal conductivity of package and board. This section de-
scribes the impact of these parameters on the junction temper-
ature and gives a guideline to estimate the MPC9448 die junc-
tion temperature and the associated device reliability. For a
complete analysis of power consumption as a function of oper-
ating conditions and associated long term device reliability
please refer to the application note AN1545. According the
AN1545, the long-term device reliability is a function of the die
junction temperature:
Table 9: Die junction temperature and MTBF
Junction temperature (
°C)
MTBF (Years)
100
20.4
110
9.1
120
4.2
130
2.0
Increased power consumption will increase the die junction
temperature and impact the device reliability (MTBF). Accord-
ing to the system-defined tolerable MTBF, the die junction tem-
perature of the MPC9448 needs to be controlled and the ther-
mal impedance of the board/package should be optimized.
The power dissipated in the MPC9448 is represented in equa-
tion 1.
Where ICCQ is the static current consumption of the
MPC9448, CPD is the power dissipation capacitance per out-
put,
(Μ)ΣCL represents the external capacitive output load, N
is the number of active outputs (N is always 12 in case of the
MPC9448). The MPC9448 supports driving transmission lines
to maintain high signal integrity and tight timing parameters.
Any transmission line will hide the lumped capacitive load at
the end of the board trace, therefore,
ΣCL is zero for controlled
transmission line systems and can be eliminated from equa-
tion 1. Using parallel termination output termination results in
equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are a
function of the output termination technique and DCQ is the
clock signal duty cyle. If transmission lines are used
ΣCL is
zero in equation 2 and can be eliminated. In general, the use of
controlled transmission line techniques eliminates the impact
of the lumped capacitive loads at the end lines and greatly
reduces the power dissipation of the device. Equation 3 de-
scribes the die junction temperature TJ as a function of the
power consumption.
Where Rthja is the thermal impedance of the package (junc-
tion to ambient) and TA is the ambient temperature. According
to Table 9, the junction temperature can be used to estimate
the long-term device reliability. Further, combining equation 1
and equation 2 results in a maximum operating frequency for
the MPC9448 in a series terminated transmission line system,
equation 4.
P
TOT +
I
CCQ ) VCC @ fCLOCK @
N
@ C
PD )
M
CL
@ V
CC
Equation 1
P
TOT + VCC @
I
CCQ ) VCC @ fCLOCK @
N
@ C
PD )
M
CL
)
P
DC
Q @ IOH @ VCC * VOH ) 1 * DCQ @ IOL @ VOL Equation 2
TJ + TA ) PTOT @ Rthja
Equation 3
f
CLOCK,MAX +
1
CPD @ N @ V2
CC
@
T
J,MAX * TA
R
thja
* I
CCQ @ VCC
Equation 4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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