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參數(shù)資料
| 型號： | MPC9447ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9447 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 296K |
| 代理商： | MPC9447ACR2 |
6
MPC9447
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
578
APPLICATION INFORMATION
Figure 3. Output Clock Stop (CLK_STOP) Timing
Diagram
CCLK0 or
CCLK1
CLK_STOP
Q0 to Q8
Driving Transmission Lines
The MPC9447 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of 17
(VCC=3.3V), the outputs can drive
either parallel or series terminated transmission lines.
For
more information on transmission lines, the reader is referred
to Motorola application note AN1091. In most high perfor-
mance clock networks, point–to–point distribution of signals is
the method of choice. In a point–to–point scheme, either se-
ries terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end
of the line with a 50
resistance to VCC÷2.
Figure 4. Single versus Dual Transmission Lines
17
IN
MPC9447
OUTPUT
BUFFER
RS = 33
ZO = 50
OutA
17
IN
MPC9447
OUTPUT
BUFFER
RS = 33
ZO = 50
OutB0
RS = 33
ZO = 50
OutB1
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9447 clock driver. For the series terminated case,
however, there is no DC current draw; thus, the outputs can
drive multiple series terminated lines. Figure 4 “Single versus
Dual Transmission Lines” illustrates an output driving a single
series terminated line versus two series terminated lines in
parallel. When taken to its extreme, the fanout of the MPC9447
clock driver is effectively doubled due to its capability to drive
multiple lines at VCC=3.3V.
Figure 5. Single versus Dual Line Termination
Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
The waveform plots in Figure 5 “Single versus Dual Line
Termination Waveforms” show the simulation results of an out-
put driving a single line versus two lines. In both cases, the
drive capability of the MPC9447 output buffer is more than suf-
ficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC9447. The output waveform in Figure 5 “Single versus
Dual Line Termination Waveforms” shows a step in the wave-
form; this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 33
se-
ries resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
RS = 33 || 33
R0 = 17
VL = 3.0 ( 25 ÷ (16.5+17+25)
= 1.28V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.5V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the situa-
tion in Figure 6 “Optimized Dual Line Termination” should be
used. In this case, the series terminating resistors are reduced
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9447D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer |
| MPC9447FA | 功能描述:時鐘緩沖器 2.5 3.3V 275MHz Clock Generator RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9447FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVCMOS 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:CLOCK DRVR 2-IN LVCMOS 32LQFP - Tape and Reel |
| MPC9448 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer |
| MPC9448AC | 功能描述:時鐘緩沖器 3.3V 900MHz Clock Generator RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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