參數(shù)資料
型號(hào): MPC9447ACR2
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 9447 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: PLASTIC, LQFP-32
文件頁(yè)數(shù): 3/7頁(yè)
文件大小: 296K
代理商: MPC9447ACR2
6
MPC9447
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
576
Table 4. Absolute Maximum Ratingsa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
-0.3
3.9
V
VIN
DC Input Voltage
-0.3
VCC + 0.3
V
VOUT
DC Output Voltage
-0.3
VCC + 0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TS
Storage temperature
-65
125
°C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these con-
ditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated condi-
tions is not implied.
Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = 40°C to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
–0.3
0.8
V
LVCMOS
VOH
Output High Voltage
2.4
V
IOH = -24 mAa
VOL
Output Low Voltage
0.55
0.30
V
IOL = 24 mA
IOL = 12 mA
ZOUT
Output Impedance
17
W
IIN
Input Currentb
±300
A
VIN = VCC or GND
ICCQ
Maximum Quiescent Supply Currentc
2.0
mA
All VCC Pins
a. The MPC9447 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmis-
sion line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC=3.3V).
b. Inputs have pull-down or pull-up resistors affecting the input current.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = –40°C to +85°C)a
Symbol
5Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
350
MHz
fmax
Output Frequency
0
350
MHz
fP,REF
Reference Input Pulse Width
1.4
ns
tr, tf
CCLK0, CCLK1 Input Rise/Fall Time
1.0b
ns
0.8 to 2.0V
tPLH/HL
Propagation Delay
CCLK0 or CCLK1 to any Q
1.3
3.3
ns
tPLZ, HZ
Output Disable Time
11
ns
tPZL, ZH
Output Enable Time
11
ns
tS
Setup Time
CCLK0 or CCLK1 to CLK_STOPc
0.0
ns
tH
Hold Time
CCLK0 or CCLK1 to CLK_STOPc
1.0
ns
tsk(O)
Output-to-Output Skew
150
ps
tsk(PP)
Device-to-Device Skew
2.0
ns
tSK(P)
DCQ
Output Pulse Skewd
Output Duty Cycle
fQ<170 MHz
45
50
300
55
ps
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tJIT(CC)
Cycle-to-cycle jitter
RMS (1
σ)
TBD
ps
a. AC characteristics apply for parallel output termination of 50
to VTT.
b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
c. Setup and hold times are referenced to the falling edge of the selected clock signal input.
d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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