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參數(shù)資料
| 型號(hào)： | MPC940LAC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, ROHS COMPLIANT, LQFP-32 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 292K |
| 代理商： | MPC940LAC |
Advanced Clock Drivers Devices
6
Freescale Semiconductor
MPC940L
Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
Figure 3. Propagation Delay (tPD) Test Reference
Figure 4. LVCMOS Propagation Delay (tPD)
Test Reference
Figure 5. Output Duty Cycle (DC)
Figure 6. Output-to-Output Skew TSK(O)
Figure 7. Output Transition Time Test Reference
Figure 8. Input Transition Time Test Reference
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC940L DUT
VTT
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC940L DUT
VTT
VCC
VCC÷2
GND
VPP
VCMR
PCLK_CLK
Q
tPD
LVCMOS_CLK
Q
VCC
VCC ÷ 2
GND
tPD
VCC
VCC ÷ 2
GND
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
DC = tP/T0 x 100%
VCC
VCC ÷ 2
GND
T0
tP
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device.
tSK(O)
VCC ÷ 2
GND
VOH
VCC ÷ 2
GND
VCC
tF
tR
VCC = 3.3 V VCC = 2.5 V
2.4
0.55
1.8 V
0.6 V
tF
tR
VCC = 3.3 V VCC = 2.5 V
2.0
0.8
1.7 V
0.7 V
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