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參數(shù)資料
| 型號： | MPC940LAC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, ROHS COMPLIANT, LQFP-32 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 292K |
| 代理商： | MPC940LAC |
Advanced Clock Drivers Devices
Freescale Semiconductor
3
MPC940L
Table 2. Absolute Maximum Ratings(1)
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is
not implied.
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
–40
125
°C
Table 3. DC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
CMOS_CLK
2.4
VCCI
V
VIL
Input LOW Voltage
CMOS_CLK
0.8
V
VPP
Peak-to-Peak Input Voltage
PECL_CLK
500
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCCI – 1.4
VCCI – 0.6
V
VOH
Output HIGH Voltage
2.4
V
IOH = –20 mA
VOL
Output LOW Voltage
0.5
V
IOL = 20 mA
IIN
Input Current
±200
A
CIN
Input Capacitance
4.0
pF
Cpd
Power Dissipation Capacitance
10
pF
per output
ZOUT
Output Impedance
18
23
28
ICC
Maximum Quiescent Supply Current
0.5
1.0
mA
Table 4. AC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
Fmax
Maximum Input Frequency
250
MHz
tPLH
Propagation Delay
PECL_CLK
≤ 150 MHz
CMOS_CLK
≤ 150 MHz
2.0
1.8
2.7
2.5
3.4
3.0
ns
tPLH
Propagation Delay
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
2.0
1.8
2.9
2.4
3.7
3.2
ns
tsk(o)
Output-to-Output Skew
PECL_CLK
CMOS_CLK
150
ps
tsk(pp)
Part-to-Part Skew
PECL_CLK
≤ 150 MHz
CMOS_CLK
≤ 150 MHz
1.4
1.2
ns
Note (1)
1. Across temperature and voltage ranges. Includes output skew.
tsk(pp)
Part-to-Part Skew
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
1.7
1.4
ns
Note (1)
tsk(pp)
Part-to-Part Skew
PECL_CLK
CMOS_CLK
850
750
ps
Note (2)
2. For specific temperature and voltage. Includes output skew.
DC
Output Duty Cycle
fCLK < 134 MHz
fCLK ≤ 250 MHz
45
40
50
55
60
%
Input DC = 50%
tr, tf
Output Rise/Fall Time
0.3
1.1
ns
0.5 – 2.4 V
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