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參數(shù)資料
| 型號： | MPC93R52ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LEAD FREE, LQFP-32 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MPC93R52ACR2 |
Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC93R52
Power Supply Filtering
The MPC93R52 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCCA (PLL) power supply impacts the
device characteristics, for instance I/O jitter. The MPC93R52
provides separate power supplies for the output buffers (VCC)
and the phase-locked loop (VCCA) of the device. The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC93R52. Figure 7 illustrates a typical power
supply filter scheme. The MPC93R52 frequency and phase
stability is most susceptible to noise with spectral content in
the 100 kHz to 20 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor RF. From the data sheet the
ICCA current (the current sourced through the VCCA pin) is
typically 3 mA (5 mA maximum), assuming that a minimum of
2.98 V must be maintained on the VCCA pin. The resistor RF
shown in Figure 7 should have a resistance of 5-25
to meet
the voltage drop criteria.
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R52 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC93R52 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC93R52. Designs using the MPC93R52 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC93R52 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a
÷4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC93R52 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC93R52 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Due to the statistical nature of I/O jitter a RMS value (1
σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 9.
Figure 7. VCCA Power Supply Filter
VCCA
VCC
MPC93R52
10 nF
RF = 5–25
CF
33...100 nF
RF
VCC
CF = 22 F
Figure 8. MPC93R52 Max. Device-to-Device Skew
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
CCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93R52FA | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93R52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC940 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
| MPC940L | 制造商:Motorola Inc 功能描述: |
| MPC940LAC | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 FSL 1-18 LVCMOS/LVPE CL to LVCMOS Fanout RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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