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參數(shù)資料
| 型號： | MPC93R52ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LEAD FREE, LQFP-32 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 337K |
| 代理商： | MPC93R52ACR2 |
Advanced Clock Drivers Devices
6
Freescale Semiconductor
MPC93R52
APPLICATIONS INFORMATION
Programming the MPC93R52
The MPC93R52 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 480 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
the various output configurations and frequency ratios
supported by the MPC93R52. See also Figure 3 to Figure 6
for further reference. A ÷2 output divider cannot be used for
feedback.
Table 7. MPC93R52 Example Configuration (F_RANGE = 0)
PLL Feedback
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 4(2)
2. QAx connected to FB_IN and FSELA=0.
50–120
0
fref
(50-120 MHz) fref
(50-120 MHz)
fref
2 (100-240 MHz)
0
1
fref
(50-120 MHz) fref
(50-120 MHz)
fref
(50-120 MHz)
1
0
fref
2÷3 (33-80 MHz) fref
(50-120 MHz)
fref
2 (100-240 MHz)
1
0
1
fref
2÷3 (33-80 MHz) fref
(50-120 MHz)
fref
(50-120 MHz)
VCO
÷ 6(3)
3. QAx connected to FB_IN and FSELA=1.
33.3–80
1
0
fref
(33-80 MHz) fref
3÷2 (50-120 MHz) fref 3 (100-240 MHz)
1
0
1
fref
(33-80 MHz) fref
3÷2 (50-120 MHz) fref 3÷2 (50-120 MHz)
1
0
fref
(33-80 MHz) fref
3 (100-240 MHz) fref 3 (100-240 MHz)
1
fref
(33-80 MHz) fref
3 (100-240 MHz) fref 3÷2 (50-120 MHz)
Table 8. MPC93R52 Example Configurations (F_RANGE = 1)
PLL Feedback
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 8(2)
2. QAx connected to FB_IN and FSELA=0.
25-60
0
fref
(25-60 MHz) fref
2 (50-120 MHz)
0
1
fref
(25-60 MHz) fref
(25-60 MHz)
1
0
fref
2÷3 (16-40 MHz) fref
(25-60 MHz) fref
2 (50-120 MHz)
1
0
1
fref
2÷3 (16-40 MHz) fref
(25-60 MHz) fref
(25-60 MHz)
VCO
÷ 12(3)
3. QAx connected to FB_IN and FSELA=1.
16.67–40
1
0
fref
(16-40 MHz) fref
3÷2 (25-60 MHz) fref 3 (50-120 MHz)
1
0
1
fref
(16-40 MHz) fref
3÷2 (25-60 MHz) fref 3÷2 (25-60 MHz)
1
0
fref
(16-40 MHz) fref
3 (50-120 MHz) fref 3 (50-120 MHz)
1
fref
(16-40 MHz) fref
3 (50-120 MHz) fref 3÷2 (25-60 MHz)
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