參數(shù)資料
型號(hào): MPC93R52AC
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: LEAD FREE, LQFP-32
文件頁數(shù): 3/13頁
文件大?。?/td> 494K
代理商: MPC93R52AC
Advanced Clock Drivers Devices
Freescale Semiconductor
11
MPC93R52
Figure 15. Propagation Delay (t(), static phase
offset) Test Reference
Figure 16. Output Duty Cycle (DC)
Figure 14. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
CCLK
FB_IN
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC ÷ 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 18. Cycle-to-Cycle Jitter
Figure 17. I/O Jitter
Figure 20. Output Transition Time Test Reference
tF
tR
VCC=3.3 V
2.4
0.55
TJIT() = |T0–T1mean|
CCLK
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
TJIT(PER) = |TN–1/f0|
T0
Figure 19. Period Jitter
MPC93R52
3.3 V 1:11 LVCMOS Zero Delay Clock Generator
NETCOM
IDT 3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93R52
11
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