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參數(shù)資料
| 型號(hào)： | MPC93R51ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DRIVER LV 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC93R51 REVISION 4 JANUARY 31, 2013
6
2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
APPLICATIONS INFORMATION
Programming the MPC93R51
The MPC93R51 clock driver outputs can be configured
into several divider modes. In addition, the external feedback
of the device allows for flexibility in establishing various input
to output frequency relationships. The output divider of the
four output groups allows the user to configure the outputs
into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
Table 7 illustrates the various output configurations. The
table describes the outputs using the input clock frequency
CLK as a reference.
The output division settings establish the output
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to
240 MHz while the VCO frequency range is specified from
200 MHz to 480 MHz and should not be exceeded for stable
operation.
Using the MPC93R51 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC93R51. For these applications the MPC93R51 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC93R51 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC93R51 PLL
allows for its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge and virtually eliminates the propagation delay through
the device.
The remaining insertion delay (skew error) of the
MPC93R51 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t()), I/O jitter
(tJIT(), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Table 7. Output Frequency Relationship(1) for an Example Configuration
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC
QD
0
2 * CLK
CLK
0
1
2 * CLK
CLK
2
0
1
0
4 * CLK
2 * CLK
CLK
2* CLK
0
1
4 * CLK
2 * CLK
CLK
0
1
0
2 * CLK
CLK
2
CLK
0
1
0
1
2 * CLK
CLK
2
CLK
2
0
1
0
4 * CLK
CLK
2 * CLK
0
1
4 * CLK
CLK
1
0
CLK
1
0
1
CLK
2
1
0
1
0
2 * CLK
CLK
2 * CLK
1
0
1
2 * CLK
CLK
1
0
CLK
2
CLK
1
0
1
CLK
2
CLK
2
1
0
2 * CLK
CLK
2 * CLK
1
2 * CLK
CLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93R51D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51FA | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC93R51FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 32LQFP - Tape and Reel |
| MPC93R52 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR |
| MPC93R52AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, pwr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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