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參數(shù)資料
| 型號： | MPC93H52ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 標準包裝： | 2,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:11 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC93H52 REVISION 5 FEBRUARY 15, 2013
9
2013 Integrated Device Technology, Inc.
MPC93H52 Data Sheet
3.3 V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Due to the statistical nature of I/O jitter a RMS value (1
)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 9.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% (
3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –445 ps to 395 ps relative to CCLK:
tSK(PP) = [–200ps...150ps] + [–200ps...200ps] +
[(15ps
–3)...(15ps 3)] + tPD, LINE(FB)
tSK(PP) = [–445ps...395ps] + tPD, LINE(FB)
Driving Transmission Lines
The MPC93H52 clock driver was designed to drive high-
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC2.
This technique draws a fairly high level of DC current and,
thus, only a single terminated line can be driven by each
output of the MPC93H52 clock driver. For the series
terminated case, however, there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 9 illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC93H52
clock driver is effectively doubled due to its capability to drive
multiple lines.
Figure 9. Single versus Dual Transmission Lines
simulation results of an output driving a single line versus two
lines. In both cases, the drive capability of the MPC93H51
output buffer is more than sufficient to drive 50
transmission lines on the incident edge. Note from the delay
measurements in the simulations, a delta of only 43 ps exists
between the two differently loaded outputs. This suggests
that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the MPC93H51.
step in the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
series resistor, plus the output
impedance, does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL =VS (Z0 (RS + R0 + Z0))
Z0 =50 || 50
RS =40 || 40
R0 =10
VL = 3.0 (25 (20 + 10 + 25)
= 1.36 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.7 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Since this step is well above the threshold region, it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 11 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
Table 9. Confidence Factor CF
CF
Probability of Clock Edge within the Distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
10
IN
MPC93H52
OUTPUT
BUFFER
RS =40
ZO = 50
OutA
10
IN
MPC93H52
OUTPUT
BUFFER
RS =40
ZO = 50
OutB0
RS = 40
ZO = 50
OutB1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51AC | 功能描述:時鐘驅(qū)動器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC93R51ACR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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