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參數(shù)資料
| 型號(hào)： | MPC93H51FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MPC93H51FAR2 |
MPC93H51 : 3.3V CMOS PLL Clock Generator and Driver
The MPC93H51 is a 3.3V compatible, PLL based clock generator targeted
for high performance clock distribution systems. With output frequencies of
up to 200 MHz and a maximum output skew of 200 ps the MPC93H51 is an
ideal solution for the most demanding clock tree designs. The device offers
9 low skew clock outputs, each is configurable to support the clocking
needs of the various high–performance microprocessors including the
PowerQuicc II integrated communication microprocessor. The extended
temperature range of the MPC93H51 supports telecommunication and
networking requirements.The devices employs a fully differential PLL
design to minimize cycle–to–cycle and long–term jitter.
MPC93H51 Features
9 outputs LVCMOS PLL clock generator
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25-200 MHz output frequency range
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3.3V compatible
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Compatible to various microprocessor such as PowerQuicc II
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Supports networking, telecommunications and computer applications
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Fully integrated PLL
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Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
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LVPECL and LVCMOS compatible inputs
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External feedback enables zero-delay configurations
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Output enable/disable and static test mode (PLL enable/disable)
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Low skew characteristics: maximum 200 ps output-to-output
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Cycle-to-cycle jitter max. ±50ps
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32 lead LQFP package
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Ambient operating temperature range of -40 to +85*C
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The MPC93H51 utilizes PLL technology to frequency and phase lock its
outputs onto an input reference clock. Normal operation of the MPC93H51
requires a connection of one of the device outputs to the EXT_FB input to
close the PLL feedback path. The reference clock frequency and the output
divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers
of divide–by–2, divide–by–4 and divide–by–8 the internal VCO of the
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MPC93H51 Product Summary Page
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC93H51&nodeId=01HGpJ52483327 (1 of 3) [7/19/2004 9:49:11 AM]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H52AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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