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參數(shù)資料
| 型號： | MPC93H51FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MPC93H51FAR2 |
MPC93H51
8
Low Voltage PLL Clock Driver
MOTOROLA
Power Supply Filtering
The MPC93H51 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Noise on the VCCA (PLL) power supply impacts the de-
vice characteristics, for instance I/O jitter. The
MPC93H51 provides separate power supplies for the
output buffers (VCC) and the phase-locked loop (VCCA) of
the device.The purpose of this design technique is to iso-
late the high switching noise digital outputs from the rela-
tively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simple but effective form
of isolation is a power supply filter on the VCCA pin for the
MPC93H51.
Figure 5 illustrates a typical power supply filter
scheme. The MPC93H51 frequency and phase stability
is most susceptible to noise with spectral content in the
100kHz to 20MHz range. Therefore the filter should be
designed to target this range. The key parameter that
needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data
sheet the ICCA current (the current sourced through the
VCCA pin) is typically 6 mA (12 mA maximum), assuming
that a minimum of 3.0V must be maintained on the VCCA
pin. The resistor RF shown in Figure 5 “VCCA Power Sup-
ply Filter” must have a resistance of 5–15
to meet the
voltage drop criteria.
As the noise frequency crosses the series resonant
point of an individual capacitor its overall impedance be-
gins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown en-
sures that a low impedance path to ground exists for fre-
quencies well above the bandwidth of the PLL. Although
the MPC93H51 has several design features to minimize
the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be
applications in which overall performance is being de-
graded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related prob-
lems in most designs.
Driving Transmission Lines
The MPC93H51 clock driver was designed to drive
high speed signals in a terminated transmission line en-
vironment. To provide the optimum flexibility to the user
the output drivers were designed to exhibit the lowest im-
pedance possible. With an output impedance of less than
20
the drivers can drive either parallel or series termi-
nated transmission lines. For more information on trans-
mission lines the reader is referred to Motorola
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the meth-
od of choice. In a point-to-point scheme either series ter-
minated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the
end of the line with a 50
resistance to VCC÷2.
This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by
each output of the MPC93H51 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 6 “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When tak-
en to its extreme the fanout of the MPC93H51 clock driv-
er is effectively doubled due to its capability to drive
multiple lines.
The waveform plots in Figure 7 “Single versus Dual
Line Termination Waveforms” show the simulation results
of an output driving a single line versus two lines. In both
cases the drive capability of the MPC93H51 output buffer
is more than sufficient to drive 50
transmission lines on
the incident edge. Note from the delay measurements in
the simulations a delta of only 43ps exists between the
Figure 5. VCCA Power Supply Filter
VCCA
VCC
MPC93H51
0.01
F
22
F
RF
VCC
0.01
F
Figure 6. Single versus Dual Transmission Lines
10
IN
MPC93H51
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
10
IN
MPC93H51
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H52AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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