參數資料
型號： MPC9352AC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 時鐘及定時
英文描述： 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： LEAD FREE, LQFP-32
文件頁數： 15/16頁
文件大?。?/td> 346K
代理商： MPC9352AC
Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC9352
APPLICATIONS INFORMATION
Programming the MPC9352
The MPC9352 supports output clock frequencies from
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
3:2 as well as 2:3, 3:1 and 2:1. Table 9 and Table 10
illustrates the various output configurations and frequency
ratios supported by the MPC9352. See also Figure 3 to
Figure 6 for further reference. A ÷2 output divider cannot be
used for feedback.
Table 9. MPC9352 Example Configuration (F_RANGE = 0)
PLL
Feedback
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 4(2)
2. QAx connected to FB_IN and FSELA=0.
50-100
0
fref
(50-100 MHz)
fref
(50-100 MHz)
fref * 2 (100-200 MHz)
0
1
fref
(50-100 MHz)
fref
(50-100 MHz)
fref
(50-100 MHz)
1
0
fref * 2
÷3 (33-66 MHz) fref
(50-100 MHz)
fref * 2 (100-200 MHz)
1
0
1
fref * 2
÷3 (33-66 MHz) fref
(50-100 MHz)
fref
(50-100 MHz)
VCO
÷ 6(3)
3. QAx connected to FB_IN and FSELA=1.
33.3-66.67
1
0
fref
(33-66 MHz)
fref * 3
÷2 (50-100 MHz) fref * 3 (100-200 MHz)
1
0
1
fref
(33-66 MHz)
fref * 3
÷2 (50-100 MHz) fref * 3÷2 (50-100 MHz)
1
0
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
1
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
fref * 3
÷2 (50-100 MHz)
Table 10. MPC9352 Example Configurations (F_RANGE = 1)
PLL Feedback
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 8(2)
2. QAx connected to FB_IN and FSELA=0.
25-50
0
fref
(25-50 MHz)
fref
(25-50 MHz)
fref * 2
(50-100 MHz)
0
1
fref
(25-50 MHz)
fref
(25-50 MHz)
fref
(25-50 MHz)
1
0
fref * 2
÷3 (16-33 MHz) fref
(25-50 MHz)
fref * 2
(50-100 MHz)
1
0
1
fref * 2
÷3 (16-33 MHz) fref
(25-50 MHz)
fref
(25-50 MHz)
VCO
÷ 12(3)
3. QAx connected to FB_IN and FSELA=1.
16.67-33.3
1
0
fref
(16-33 MHz)
fref * 3
÷2 (25-50 MHz) fref * 3 (50-100 MHz)
1
0
1
fref
(16-33 MHz)
fref * 3
÷2 (25-50 MHz) fref * 3÷2 (25-50 MHz)
1
0
fref
(16-33 MHz)
fref * 3
(50-100 MHz) fref * 3
(50-100 MHz)
1
fref
(16-33 MHz)
fref * 3
(50-100 MHz) fref * 3
÷2 (25-50 MHz)
相關PDF資料
PDF描述
MPC9352ACR2 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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相關代理商/技術參數
參數描述
MPC9352ACR2 功能描述:時鐘發(fā)生器及支持產品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9352FA 功能描述:鎖相環(huán) - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MPC9352FAR2 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel
MPC93H51AC 功能描述:時鐘發(fā)生器及支持產品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MPC93H51ACR2 功能描述:時鐘發(fā)生器及支持產品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
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