參數(shù)資料
型號(hào): MPC9352AC
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 5/16頁(yè)
文件大小: 0K
描述: IC CLK GEN ZD 1:11 32-LQFP
標(biāo)準(zhǔn)包裝: 250
類型: PLL 時(shí)鐘發(fā)生器
PLL: 帶旁路
輸入: LVCMOS
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:11
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 200MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
MPC9352 REVISION 8 JANUARY 31, 2013
13
2013 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Figure 15. Propagation Delay (t(), static phase
offset) Test Reference
Figure 16. Output Duty Cycle (DC)
Figure 14. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
VCC
VCC 2
GND
VCC
VCC 2
GND
tSK(O)
VCC
VCC 2
GND
VCC
VCC 2
GND
t()
CCLK
FB_IN
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
VCC
VCC 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 18. Cycle-to-Cycle Jitter
Figure 17. I/O Jitter
Figure 20. Output Transition Time Test Reference
tF
tR
VCC=3.3 V
VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
TJIT() = |T0–T1mean|
CCLK
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles.
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
TJIT(PER) = |TN–1/f0|
T0
Figure 19. Period Jitter
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