- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2014 > MPC9352AC (IDT, Integrated Device Technology Inc)IC CLK GEN ZD 1:11 32-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC9352AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:11 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MPC9352 REVISION 8 JANUARY 31, 2013
7
2013 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
APPLICATIONS INFORMATION
Programming the MPC9352
The MPC9352 supports output clock frequencies from
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
illustrates the various output configurations and frequency
ratios supported by the MPC9352. See also Figure 3 to
Figure 6 for further reference. A 2 output divider cannot be
used for feedback.
tJIT()
I/O Phase Jitter
4 feedback divider RMS (1 )(7)
6 feedback divider RMS (1 )
8 feedback divider RMS (1 )
12 feedback divider RMS (1 )
15
20
18 – 20
25
ps
BW
PLL closed loop bandwidth(8)
4 feedback
6 feedback
8 feedback
12 feedback
1.0 – 8.0
0.7 – 3.0
0.5 – 2.5
0.4 – 1.0
MHz
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50
to VTT.
2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a
2 divider for feedback.
3. In PLL bypass mode, the MPC9352 divides the input reference clock.
4. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO FB.
6. See application section for part-to-part skew calculation.
7. See application section for a jitter calculation for other confidence factors than 1
.
8. -3 dB point of PLL transfer characteristics.
Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)(1) (Continued)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Table 9. MPC9352 Example Configuration (F_RANGE = 0)
PLL
Feedback
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
4(2)
2. QAx connected to FB_IN and FSELA=0.
50-100
0
fref
(50-100 MHz)
fref
(50-100 MHz)
fref * 2 (100-200 MHz)
0
1
fref
(50-100 MHz)
fref
(50-100 MHz)
fref
(50-100 MHz)
1
0
fref * 2
3 (33-66 MHz) fref
(50-100 MHz)
fref * 2 (100-200 MHz)
1
0
1
fref * 2
3 (33-66 MHz) fref
(50-100 MHz)
fref
(50-100 MHz)
VCO
6(3)
3. QAx connected to FB_IN and FSELA=1.
33.3-66.67
1
0
fref
(33-66 MHz)
fref * 3
2 (50-100 MHz) fref * 3 (100-200 MHz)
1
0
1
fref
(33-66 MHz)
fref * 3
2 (50-100 MHz) fref * 32 (50-100 MHz)
1
0
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
1
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
fref * 3
2 (50-100 MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC93H51AC | IC PLL CLK DRIVER LV 32-LQFP |
| MPC93H52AC | IC CLK GEN ZD 1:11 32-LQFP |
| MPC93R51AC | IC PLL CLK DRIVER LV 32-LQFP |
| MPC9608AC | IC CLOCK BUFFER ZD 1:10 32-LQFP |
| MPC962309EJ-1H | IC BUFFER ZD 1:5 3.3V 16-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9352ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9352FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93H51AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H51ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。