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參數(shù)資料
| 型號(hào)： | MPC9350AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MPC9350 REVISION 7 DECEMBER 19, 2012
6
2012 Integrated Device Technology, Inc.
MPC9350 Data Sheet
Low Voltage PLL Clock Driver
APPLICATIONS INFORMATION
Programming the MPC9350
The MPC9350 clock driver outputs can be configured into
several divider modes. In addition, the internal feedback of
the device allows for flexibility in establishing two input to
output frequency relationships. The output division settings
establish the output frequency relationship. The output
divider of the four output groups allows the user to configure
the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The
use of even dividers ensures that the output duty cycle is
configurations. The tables describe the outputs using the
input clock frequency CLK as a reference.
In addition, it must be ensured that the VCO will be stable
given the frequency of the outputs desired. The feedback
frequency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 25 MHz to 200 MHz while
the VCO frequency range is specified from 200 MHz to
400 MHz and should not be exceeded for stable operation.
Table 7. Output Frequency Relationship(1) FBSEL = 0, (VC0 = 32 * CLK)
1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output
relationships in external feedback mode.
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC0, QC1
QD0–QD4
0
16 * CLK
8 * CLK
0
1
16 * CLK
8 * CLK
4 * CLK
0
1
0
16 * CLK
8 * CLK
4 * CLK
8 * CLK
0
1
16 * CLK
8 * CLK
4 * CLK
0
1
0
16 * CLK
4 * CLK
8 * CLK
0
1
0
1
16 * CLK
4 * CLK
8 * CLK
4 * CLK
0
1
0
16 * CLK
4 * CLK
8 * CLK
0
1
16 * CLK
4 * CLK
1
0
8 * CLK
1
0
1
8 * CLK
4 * CLK
1
0
1
0
8 * CLK
4 * CLK
8 * CLK
1
0
1
8 * CLK
4 * CLK
1
0
8 * CLK
4 * CLK
8 * CLK
1
0
1
8 * CLK
4 * CLK
8 * CLK
4 * CLK
1
0
8 * CLK
4 * CLK
8 * CLK
1
8 * CLK
4 * CLK
Table 8. Output Frequency Relationship(1) FBSEL = 1, (VC0 = 16 * CLK)
1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output
relationships in external feedback mode.
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC0, QC1
QD0–QD4
0
8 * CLK
4 * CLK
0
1
8 * CLK
4 * CLK
2 * CLK
0
1
0
8 * CLK
4 * CLK
2 * CLK
4 * CLK
0
1
8 * CLK
4 * CLK
2 * CLK
0
1
0
8 * CLK
2 * CLK
4 * CLK
0
1
0
1
8 * CLK
2 * CLK
4 * CLK
2 * CLK
0
1
0
8 * CLK
2 * CLK
4 * CLK
0
1
8 * CLK
2 * CLK
1
0
4 * CLK
1
0
1
4 * CLK
2 * CLK
1
0
1
0
4 * CLK
2 * CLK
4 * CLK
1
0
1
4 * CLK
2 * CLK
1
0
4 * CLK
2 * CLK
4 * CLK
1
0
1
4 * CLK
2 * CLK
4 * CLK
2 * CLK
1
0
4 * CLK
2 * CLK
4 * CLK
1
4 * CLK
2 * CLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9350ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9350D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350FA | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9350FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC9351 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low Voltage PLL Clock Driver |
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