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參數(shù)資料
| 型號(hào)： | MPC9350AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類(lèi)型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:9 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤(pán) |
MPC9350 REVISION 7 DECEMBER 19, 2012
3
2012 Integrated Device Technology, Inc.
MPC9350 Data Sheet
Low Voltage PLL Clock Driver
Table 1. Pin Description
Number
Name
Type
Description
XTAL1, XTAL2
Input
Analog
Crystal oscillator terminals
TCLK
Input
LVCMOS
Single ended reference clock signal or test clock
FBSEL
Input
LVCMOS
Selects feedback divider ratio
REF_SEL
Input
LVCMOS
Selects input reference source
FSELA
Input
LVCMOS
Output A divider selection
FSELB
Input
LVCMOS
Output B divider selection
FSELC
Input
LVCMOS
Outputs C divider selection
FSELD
Input
LVCMOS
Outputs D divider selection
OE
Input
LVCMOS
Output enable/disable
QA
Output
LVCMOS
Bank A clock output
QB
Output
LVCMOS
Bank B clock output
QC0, QC1
Output
LVCMOS
Bank C clock outputs
QD0 – QD4
Output
LVCMOS
Bank D clock outputs
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
Positive power supply for the PLL
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
Selects XTAL
Selects TCLK
PLL_EN
1
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
PLL enabled. The VCO output is routed to the
output dividers
FBSEL
0
Selects feedback divider
32
VCO = 32 * Input reference clock
Selects feedback divider
16
VCO = 16 * Input reference clock
OE
0
Outputs enabled
Outputs disabled
FSELA
0
QA = VCO
2
QA = VCO
4
FSELB
0
QB = VCO
4
QB = VCO
8
FSELC
0
QC = VCO
4
QC = VCO
8
FSELD
0
QD = VCO
4
QD = VCO
8
Table 3. Absolute Maximum Ratings(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VIN
DC Input Voltage
–0.3
VCC+0.3
V
VOUT
DC Output Voltage
–0.3
VCC+0.3
V
IIN
DC Input Current
20
mA
IOUT
DC Output Current
50
mA
TS
Storage temperature
–40
125
°C
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| MPC9350ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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| MPC9351 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Low Voltage PLL Clock Driver |
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