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參數(shù)資料
| 型號： | MPC92474AC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LEAD FREE, LQFP-48 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 814K |
| 代理商： | MPC92474AC |
Advanced Clock Drivers Devices
4
Freescale Semiconductor
MPC92474
PREL
IM
IN
AR
Y
S_DATA
Input
0
LVCMOS
Serial configuration data input.
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input.
M[0:8]
Input
000100000
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
NA[2:0]
Input
011
LVCMOS
Parallel configuration for Post-PLL divider (NA).
N is sampled on the low-to-high transition of P_LOAD.
NB[2:0]
Input
011
LVCMOS
Parallel configuration for Post-PLL divider (NB).
N is sampled on the low-to-high transition of P_LOAD.
P_DIV
Input
M
LVCMOS
Prescale divider (P) configuration.
OE_A
Input
1
LVCMOS
Output enable (active high) for FOUTA0.
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state
(FOUT = L, FOUT = H).
OE_B
Input
1
LVCMOS
Output enable (active high) for FOUTB0.
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state
(FOUT = L, FOUT = H).
OE_REF
Input
0
LVCMOS
Output enable (active high) for REF_CLK.
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state
(FOUT = L, FOUT = H).
VCO_SEL
Input
1
LVCMOS
PLL bypass selected when = 0. Normal operation when = 1.
MR
Input
0
LVCMOS
Device reset, active high.
GND
Supply
Ground
Negative power supply (GND).
VCC
Supply
VCC
Positive power supply for core. All VCC pins must be connected to the positive
power supply for correct operation.
VCCOA
Supply
VCC
Positive power supply for A bank output. All VCC pins must be connected to the
positive power supply for correct operation.
VCCOB
Supply
VCC
Positive power supply for B bank output. All VCC pins must be connected to the
positive power supply for correct operation.
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply).
1. A 0 represents an internal pulldown. A 1 represents an internal pullup. A M represents pulldown and pullup Vcc/2 biasing.
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Division
Output Frequency Range
0
1
560 - 700 MHz
0
1
2
280 - 350 MHz
0
1
0
3
186.66 - 233.33 MHz
0
1
4
140 - 175 MHz
1
0
5
112 - 140 MHz
1
0
1
6
93.33 - 116.66 MHz
1
0
8
70 - 87.5 MHz
1
16
35 - 43.75 MHz
Table 1. Pin Configurations (Continued)
Pin
I/O
Default(1)
Type
Function
MPC92474
LVPECL Clock Synthesizer w/Spread Spectrum
NETCOM
IDT LVPECL Clock Synthesizer w/Spread Spectrum
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC92474
4
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