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參數(shù)資料
| 型號(hào)： | MPC859TTSD |
| 廠(chǎng)商： | Motorola, Inc. |
| 英文描述： | PowerQUICC⑩ Family Technical Summary |
| 中文描述： | ⑩家庭技術(shù)的PowerQUICC綜述 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | MPC859TTSD |
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MPC859P/859T/859DSL PowerQUICC Family Technical Summary
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
PCMCIA Controller
1.4
PCMCIA Controller
The PCMCIA interface is a master (socket) controller and is compliant with release 2.1. The interface
supports up to two independent PCMCIA sockets requiring only external transceivers/buffers. The interface
provides eight memory or I/O windows where each window can be allocated to a particular socket. If only
one PCMCIA port is used, the unused port may be used as general-purpose input with interrupt capability.
On the MPC859DSL, PCMCIA support is provided on Port B only.
1.5
Power Management
The MPC859P/859T/859DSL Family supports two power management features including Normal High
and Normal Low Power Modes. Full on mode leaves the MPC8 processor fully powered with all internal
units operating at the full processor speed. A gear mode is determined by a clock divider, allowing the
operating system to reduce the processor’s operational frequency and operate in Normal Low Mode.
1.6
Communications Processor Module (CPM)
The MPC859P/859T/859DSL Family is the next generation MPC8xx family of devices. Like its
predecessor it implements a dual-processor architecture, which provides both a high-performance,
general-purpose processor for application programming use as well as a special-purpose communication
processor (CPM) uniquely designed for communications applications.
The CPM contains features that, like its predecessor, allow the MPC859P/859T/859DSL Family to excel in
communications and networking products. These features are grouped as follows:
Communications processor (CP)
Ten independent DMA (SDMA) controllers on the MPC859T; eight independent DMA (SDMA)
controllers on the MPC859DSL
Four general-purpose timers
The CP provides the communication features of the MPC859P/859T/859DSL. Included are a RISC
processor, one serial communication controller (SCC1), two serial management controllers (SMCs), a serial
peripheral interface (SPI), an I
C interface, 8 Kbytes of dual-port RAM, an interrupt controller, a time-slot
assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and ten serial
DMA channels to support the SCC, SMCs, SPI, and I
2
2
C.
The SDMAs provide two channels of general-purpose DMA capability for each communications channel.
They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic.
The four general-purpose timers on the CPM are identical to the timers found on all of the MPC8xx devices,
and supporting the internal cascading of two timers to form a 32-bit timer.
1.7
ATM Capabilities
The MPC859P/859T/859DSL Family can be used as an adaptable ATM controller suited for a variety of
applications, including the following:
DSLAM Line Cards
Access Concentrators
LAN/WAN Switches
F
Freescale Semiconductor, Inc.
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