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參數(shù)資料
| 型號： | MPC859TTS |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerQUICC⑩ Family Technical Summary |
| 中文描述： | ⑩家庭技術(shù)的PowerQUICC綜述 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 287K |
| 代理商： | MPC859TTS |
6
MPC859P/859T/859DSL PowerQUICC Family Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MOTOROLA
Embedded MPC8xx Core
The MPC859P/859T/859DSL Family is comprised of three modules that each use the 32-bit internal bus:
the MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). The
MPC859P/859T/859DSL block diagram is shown in Figure 1
.
1
The MPC859P has a 16 Kbyte Instruction Cache and a 8 Kbyte Data Cache.
The MPC859DSL does not contain SMC2 nor the Time Slot Assigner, and provides eight SDMA controllers.
2
Figure 1. MPC859P/859T/859DSLBlock Diagram
1.2
Embedded MPC8xx Core
The MPC859P/859T/859DSL Family integrates an embedded MPC8xx core with high-performance,
low-power peripherals to extend the Motorola data communications family of embedded processors farther
into high-end communications and networking products.
The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC architecture.
It has an integer unit (IU) and a load/store unit (LSU) that execute all integer and load/store operations in
hardware. The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware.
The core interface to the internal and external buses is 32 bits.
Bus
System Interface Unit (SIU)
Embedded
MPC8xx
Processor
Core
Parallel I/O
Memory Controller
4
Timers
Interrupt
Controllers
8-Kbyte
Dual-Port RAM
10 Virtual
Serial 2
and
2
Independent
DMA
Channels
System Functions
PCMCIA-ATA Interface
4-Kbyte 1
Instruction Cache
32-Entry ITLB
Instruction MMU
4-Kbyte 1
Data Cache
32-Entry DTLB
Data MMU
Instruction
Bus
Load/Store
Bus
Unified
4 Baud Rate
Generators
Parallel Interface Port
and UTOPIA
Internal
Bus Interface
Unit
External
Bus Interface
Unit
Timers
32-Bit RISC Controller
and Program
ROM
SCC1
Serial Interface
I2C
SPI
SMC2 2
SMC1
Time Slot Assigner*
DMAs
FIFOs
10/100
Base-T
Media Access
Control
MII
Fast Ethernet
Controller
F
n
.
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