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| 型號(hào)： | MPC855TCVR50D4 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 14/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC 50MHZ 357PBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤(pán) |
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8
MPC855T Communications Controller Technical Summary
MOTOROLA
MPC855T Architecture Overview
branch prediction with conditional prefetch, but without conditional execution. The embedded core can
operate on 32-bit external operands with one bus cycle.
The integer unit supports 32- x 32-bit xed-point general-purpose registers. It can execute one integer
instruction each clock cycle. Each element in the integer unit is clocked only when valid data is present in
the data queue ready for operation. This assures that the power consumption of the device is held to the
absolute minimum required to perform an operation.
The embedded core is integrated with MMUs as well as 4-Kbyte instruction and data caches. Each MMU
provides a 32-entry, fully-associative instruction and data TLB, with multiple page sizes of: 4 Kbytes, 16
Kbytes, 512 Kbytes, 256 Kbytes, and 8 Mbytes. It supports 16 virtual address spaces with 8 protection
groups. Three special registers are available as scratch registers to support software tablewalk and update.
The instruction cache is 4 Kbytes, two-way, set associative with physical addressing. It allows single-cycle
access on hit with no added latency for miss. It has four words per line, and supports burst linell using least
recently used (LRU) replacement. The cache may be locked on a per-line basis for application-critical
routines.
The data cache is 4 Kbytes, two-way, set associative with physical addressing. It allows single-cycle access
on hit with one added clock latency for miss. It has four words per line, supporting burst linell using LRU
replacement. The cache may be locked on a per-line basis for application-critical routines. The data cache
can be programmed to support copy-back or write-through via the MMU. The cache-inhibit mode can be
programmed per MMU page.
The embedded core with its instruction and data caches delivers approximately 106 MIPS at 80 MHz, using
Dhrystone 2.1, based on the assumption that it is issuing one instruction per cycle with a cache hit rate of
94%.
The embedded core provides a much improved debug interface that operates without causing any
degradation in the speed of user operations. This interface supports six watchpoint signals that are used to
detect software events. Internally the MPC855T has eight comparators, four of which operate on the
effective address on the address bus. The remaining four comparators are split, with two comparators
operating on the effective address on the data bus, and two comparators operating on the data on the data
bus. The embedded core can compare using =,
≠, <, > conditions to generate watchpoints. Each watchpoint
can then generate a breakpoint that can be programmed to trigger in a programmable number of events.
1.2.2
Fast Ethernet Controller (FEC)
The Fast Ethernet controller on the MPC855T is compliant with the IEEE 802.3u specication for 10-Mbps
and 100-Mbps connectivity. Full-duplex 100-Mbps operation is supported at system clock rates of 50 MHz
and higher. A 33-MHz system clock supports 10-Mbps operation or half-duplex 100-Mbps operation.
The Fast Ethernet controller provides greatly reduced bus utilization through the use of bursting DMA.
Optimization of bus utilization allows the MPC855T to be used in systems with low-cost memories such as
synchronous DRAM.
Transmit and receive FIFOs further reduce bus utilization by localizing all collisions to the Fast Ethernet
controller. On the transmit side, a full collision window of transmit frame data is maintained in the FIFO,
eliminating the need for repeated DMA over the system bus in the event of a collision. On the receive side,
a full collision window of data is received before any receive data is transferred into system memory,
allowing the FIFO to be ushed in the event of a runt or collided frame, with no DMA activity. However,
external memory for data buffers and buffer descriptors is required; on-chip FIFOs are only designed to
compensate for collisions and for system bus latency.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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