• <ins id="ghzjx"><label id="ghzjx"></label></ins>
    • <small id="ghzjx"></small>
    • <nobr id="ghzjx"><sup id="ghzjx"></sup></nobr>
    <ins id="ghzjx"><noframes id="ghzjx"></noframes></ins>
  • <label id="ghzjx"><dfn id="ghzjx"></dfn></label>
            


    
    



    

    
  
    
    
    
    
  
    
  
  

    





    


    
 
 




 
 


    

    
    


    參數(shù)資料
    

    


    


    
型號(hào)：
MPC8555ECPXAJD

    

    
廠商：
Freescale Semiconductor

    

    
文件頁(yè)數(shù)：
76/88頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC MPU POWERQUICC III 783-FCPBGA

    

    
標(biāo)準(zhǔn)包裝：
36

    

    
系列：
MPC85xx

    

    
處理器類(lèi)型：
32-位 MPC85xx PowerQUICC III
    		

    

    
速度：
533MHz
    		

    

    
電壓：
1.2V
    		

    

    
安裝類(lèi)型：
表面貼裝
    		

    

    
封裝/外殼：
783-BBGA，F(xiàn)CBGA
    		

    

    
供應(yīng)商設(shè)備封裝：
783-FCPBGA（29x29）
    		

    

    
包裝：
托盤(pán)
    		

    

    
配用：
CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
    		

    

    

    

	
    
    
    

    
    
	
    MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
    78
    Freescale Semiconductor
    System Design Information
    17 System Design Information
    This section provides electrical and thermal design recommendations for successful application of the
    MPC8555E.
    17.1
    System Clocking
    The MPC8555E includes five PLLs.
    1. The platform PLL (AVDD1) generates the platform clock from the externally supplied SYSCLK
    input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL
    ratio configuration bits as described in Section 15.2, “Platform/System PLL Ratio.”
    2. The e500 Core PLL (AVDD2) generates the core clock as a slave to the platform clock. The
    frequency ratio between the e500 core clock and the platform clock is selected using the e500
    PLL ratio configuration bits as described in Section 15.3, “e500 Core PLL Ratio.”
    3. The CPM PLL (AVDD3) is slaved to the platform clock and is used to generate clocks used
    internally by the CPM block. The ratio between the CPM PLL and the platform clock is fixed and
    not under user control.
    4. The PCI1 PLL (AVDD4) generates the clocking for the first PCI bus.
    5. The PCI2 PLL (AVDD5) generates the clock for the second PCI bus.
    17.2
    PLL Power Supply Filtering
    Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
    AVDD2, AVDD3, AVDD4, and AVDD5 respectively). The AVDD level should always be equivalent to VDD,
    and preferably these voltages are derived directly from VDD through a low frequency filter scheme such
    as the following.
    There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
    provide five independent filter circuits as illustrated in Figure 50, one to each of the five AVDD pins. By
    providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
    other is reduced.
    This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
    range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
    Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
    of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
    single large value capacitor.
    Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
    noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
    pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
FMC26DREH-S93
CONN EDGECARD 52POS .100 EYELET

    

    
MPC8541ECPXALF
IC MPU POWERQUICC III 783-FCPBGA

    

    
MPC8555EVTALF
IC MPU POWERQUICC III 783-FCPBGA

    

    
65801-025LF
CLINCHER RECEPTACLE ASS'-Y-TIN

    

    
MPC8536BVTATHA
MPU PWRQUICC III 1250MHZ 783PBGA

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
MPC8555ECPXALF
功能描述:微處理器 - MPU PQ 37 LITE 8555E

 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324

    

    
MPC8555ECVTAJD
功能描述:微處理器 - MPU PQ 37 LITE 8555E

 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324

    

    
MPC8555ECVTALF
功能描述:微處理器 - MPU PQ 37 LITE 8555E

 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324

    

    
MPC8555EPXAJD
功能描述:微處理器 - MPU PQ 37 LITE 8555E

 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324

    

    
MPC8555EPXAKE
功能描述:微處理器 - MPU PQ 37 LITE 8555E

 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324

    

    
    
    
    
	
    	
    
    
     
     
    發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。
    
 
     
    

   	  
    
     

    
                    			    				      
    
                
    
                  
    
                    
                    
    
                      
    
                      
                      
    采購(gòu)需求
      (若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)
    
                      
                      
    發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)
    
                      
                      
    發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)
    
                       
                        
    
                                
                                
    
                                    *型號(hào)
                                    *數(shù)量
                                    廠商
                                    批號(hào)
                                    封裝
                                  
    
                                    
                                
                                
    
                                    
                                        
    
                                            
                                            
                                        
    
                                        		
                                     
                                    
                                        
    
                                        		
                                    
                                        
    
                                        		
                                    
                                        
    
                                        		
                                    
                                        
    
                                        		
                                  
    
                                  
                                   
                                    
                            
    
                             
                             
							                            
    
                          添加更多采購(gòu)
    
                      
    
                      
                      
    
                      
                      
    我的聯(lián)系方式
    
                     
                     
                       
    
                                
                                
                                
    
                                    
                                         *
                                    
                                    
                                  
    
                                  
                                  
    
                                    
                                         *
                                    
                                    
                                  
    
                                  
                                  
    
                                    
                                        
                                    
                                    
                                  
    
                                  
                                  
    
                                    
                                         *