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    參數(shù)資料
    型號: MPC8555ECPXAJD
    廠商: Freescale Semiconductor
    文件頁數(shù): 67/88頁
    文件大?。?/td> 0K
    描述: IC MPU POWERQUICC III 783-FCPBGA
    標(biāo)準(zhǔn)包裝: 36
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 533MHz
    電壓: 1.2V
    安裝類型: 表面貼裝
    封裝/外殼: 783-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
    包裝: 托盤
    配用: CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
    MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
    Freescale Semiconductor
    7
    Overview
    – 10 Mbps IEEE 802.3 MII
    – 1000 Mbps IEEE 802.3z TBI
    – 10/100/1000 Mbps RGMII/RTBI
    — Full- and half-duplex support
    — Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
    programming models
    — 9.6-Kbyte jumbo frame support
    — RMON statistics support
    — 2-Kbyte internal transmit and receive FIFOs
    — MII management interface for control and status
    — Programmable CRC generation and checking
    OCeaN switch fabric
    — Three-port crossbar packet switch
    — Reorders packets from a source based on priorities
    — Reorders packets to bypass blocked packets
    — Implements starvation avoidance algorithms
    — Supports packets with payloads of up to 256 bytes
    Integrated DMA controller
    — Four-channel controller
    — All channels accessible by both local and remote masters
    — Extended DMA functions (advanced chaining and striding capability)
    — Support for scatter and gather transfers
    — Misaligned transfer capability
    — Interrupt on completed segment, link, list, and error
    — Supports transfers to or from any local memory or I/O port
    — Selectable hardware-enforced coherency (snoop/no-snoop)
    — Ability to start and flow control each DMA channel from external 3-pin interface
    — Ability to launch DMA from single write transaction
    PCI Controllers
    — PCI 2.2 compatible
    — One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz
    — Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one
    can be an agent
    — 64-bit dual address cycle (DAC) support
    — Supports PCI-to-memory and memory-to-PCI streaming
    — Memory prefetching of PCI read accesses
    — Supports posting of processor-to-PCI and PCI-to-memory writes
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