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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MPC8545EVTAQGB
寤犲晢锛� Freescale Semiconductor
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鎻忚堪锛� MPU POWERQUICC III 783-PBGA
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绯诲垪锛� MPC85xx
铏曠悊鍣ㄩ鍨嬶細 32-浣� MPC85xx PowerQUICC III
閫熷害锛� 1.0GHz
闆诲锛� 1.1V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 783-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 783-FCPBGA锛�29x29锛�
鍖呰锛� 鎵樼洡
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
100
Freescale Semiconductor
Package Description
I2C interface
IIC1_SCL
AG22
I/O
OVDD
4, 27
IIC1_SDA
AG21
I/O
OVDD
4, 27
IIC2_SCL
AG15
I/O
OVDD
4, 27
IIC2_SDA
AG14
I/O
OVDD
4, 27
SerDes
SD_RX[0:7]
M28, N26, P28, R26, W26, Y28, AA26, AB28
I
XVDD
鈥�
SD_RX[0:7]
M27, N25, P27, R25, W25, Y27, AA25, AB27
I
XVDD
鈥�
SD_TX[0:7]
M22, N20, P22, R20, U20, V22, W20, Y22
O
XVDD
鈥�
SD_TX[0:7]
M23, N21, P23, R21, U21, V23, W21, Y23
O
XVDD
鈥�
SD_PLL_TPD
U28
O
XVDD
24
SD_REF_CLK
T28
I
XVDD
3
SD_REF_CLK
T27
I
XVDD
3
Reserved
AC1, AC3
鈥�
2
Reserved
M26, V28
鈥�
32
Reserved
M25, V27
鈥�
34
Reserved
M20, M21, T22, T23
鈥�
38
General-Purpose Output
GPOUT[24:31]
K26, K25, H27, G28, H25, J26, K24, K23
O
BVDD
鈥�
System Control
HRESET
AG17
I
OVDD
鈥�
HRESET_REQ
AG16
O
OVDD
29
SRESET
AG20
I
OVDD
鈥�
CKSTP_IN
AA9
I
OVDD
鈥�
CKSTP_OUT
AA8
O
OVDD
2, 4
Debug
TRIG_IN
AB2
I
OVDD
鈥�
TRIG_OUT/READY/QUIESCE
AB1
O
OVDD
6, 9,
19, 29
MSRCID[0:1]
AE4, AG2
O
OVDD
5, 6, 9
MSRCID[2:4]
AF3, AF1, AF2
O
OVDD
6, 19,
29
MDVAL
AE5
O
OVDD
6
CLK_OUT
AE21
O
OVDD
11
Table 71. MPC8548E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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MPC8545EVTATGA 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU PQ3 8545E Imaging Processor RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MPC8545EVTATGB 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU FG PQ38 8548 PB Free RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MPC8545EVTATGC 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU REV2.1.3 FG Part RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
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