參數(shù)資料
型號： MPC8544CVTAQGB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù)： 42/120頁
文件大小： 1321K
代理商： MPC8544CVTAQGB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
28
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 8. SGMII Transmitter DC Measurement Circuit
8.4
SGMII AC Timing Specifications
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver
characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver
inputs (SD2_RX[n] and SD2_RX[n]) as depicted in Figure 10, respectively.
Table 25. DC Receiver Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply Voltage
VDD_SRDS2
0.9
1.0
1.05
V
—
DC input voltage range
—
1
Input differential voltage
LSTS = 0
Vrx_diffpp
100
—
1200
mV
2, 4
LSTS = 1
175
—
Loss of signal threshold
LSTS = 0
Vlos
30
—
100
mV
3, 4
LSTS = 1
65
—
175
Input AC common mode voltage
Vcm_acpp
——
100
mV
5.
Receiver differential input impedance
Zrx_diff
80
—
120
Ω
—
Receiver common mode input impedance
Zrx_cm
20
—
35
Ω
—
Common mode input voltage
Vcm
xcorevss
—
xcorevss
V
6
Notes:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. Refer to
4. The LSTS shown in this table refers to the LSTSCD bit field of MPC8544E SerDes 2 control register 1.
5. VCM_ACp-p is also referred to as peak-to-peak AC common mode voltage.
6. On-chip termination to SGND_SRDS2 (xcorevss).
50
Ω
Transmitter
SD2_TX
n
SD2_TX
n
50
Ω
Vos
VOD
MPC8544E SGMII
SerDes Interface
50
Ω
50
Ω
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