參數(shù)資料
型號: MPC8544CVTAQGB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù): 29/120頁
文件大小: 1321K
代理商: MPC8544CVTAQGB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
16
Freescale Semiconductor
RESET Initialization
For FIFO encoded mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more
than 167 MHz.
4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8544E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM
component(s).
Table 9 provides the PLL lock times.
Table 8. RESET Initialization Timing Specifications1
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HREST
100
μs—
Minimum assertion time for SRESET
3
SYSCLKs
1
PLL input setup time with stable SYSCLK before HRESET
negation
100
μs—
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with
respect to negation of HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
5
SYSCLKs
1
Note:
1. SYSCLK is the primary clock input for the MPC8544E.
Table 9. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
Core and platform PLL lock times
100
μs—
Local bus PLL
50
μs—
PCI bus lock time
50
μs—
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