參數(shù)資料
型號(hào): MPC8544CVTAQGA
廠商: Freescale Semiconductor
文件頁數(shù): 88/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
72
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 54. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
16.2.4.1
Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
16.3
SerDes Transmitter and Receiver Reference Circuits
Figure 55 shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 55. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in the section below (PCI Express or
SGMII) in this document based on the application usage:
Please note that external AC Coupling capacitor is required for the above serial transmission protocols
with the capacitor value defined in specification of each protocol section.
SDn_REF_CLK
VCROSS MEDIAN
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN – 100 mV
TFALL
TRISE
50
Ω
Receiver
Transmitter
50
Ω
50
Ω
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
50
Ω
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
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