- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45369 > MPC8544AVTAQG (FREESCALE SEMICONDUCTOR INC) 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC8544AVTAQG |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783 |
| 文件頁數(shù)： | 127/128頁 |
| 文件大小： | 1411K |
| 代理商： | MPC8544AVTAQG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁當(dāng)前第127頁第128頁
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
98
Freescale Semiconductor
Package Description
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 K
Ω) be placed on this pin to OVDD.
3. This pin must always be pulled high.
4. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pull-up or active driver is needed. TSEC3_TXD[3] (cfg_srds_sgmii_refclk) is an exception, because the
default value of this configuration signal is low (0). Thus, no external pull-down resistor is needed for selecting the default
configuration value.
5. Treat these pins as no connects (NC) unless using debug address functionality.
6. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ω pull-up or pull-down
resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.”
7. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-k
Ω
pull-up or pull-down resistors. See Section 19.3, “e500 Core PLL Ratio.”
8. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. Therefore, this pin will be described as an I/O for boundary scan.
9. For proper state of these signals during reset, DMA_DACK[1] must be pulled down to GND through a resistor.
DMA_DACK[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down
the value of the net at reset, then a pullup is needed on DMA_DACK[0].
10. This output is actively driven during reset rather than being three-stated during reset.
11. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
12. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
13. Anode and cathode of internal thermal diode.
14. Treat pins AC7, T5, V2, and M7 as spare configuration pins cfg_spare[0:3]. The spare pins are unused POR config pins. It
is highly recommended that the customer provide the capability of setting these pins low (that is, pull-down resistor which
is not currently stuffed) in order to support new config options should they arise between revisions.
15. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
during reset.
16. This pin is only an output in FIFO mode when used as Rx flow control.
17. Do not connect.
18. These are test signals for factory use only and must be pulled up (100
Ω to 1 kΩ) to OVDD for normal machine operation.
19. Independent supplies derived from board VDD.
20. Recommend a pull-up resistor (1 K~) be placed on this pin to OVDD.
21. The following pins must not be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE,
MSRCID[2:4], and ASLEEP.
22. This pin requires an external 4.7-k
Ω pull-down resistor to prevent PHY from seeing a valid transmit enable before it is
actively driven.
23. General-purpose POR configuration of user system.
Table 63. MPC8544EPinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8544EAVTAQG | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783 |
| MPC8544EVTANG | 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783 |
| MPC8544ECVTARJ | 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA783 |
| MPC8544EVTAQG | 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 |
| MPC8544EVTARJ | 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8544AVTAQGA | 制造商:Freescale Semiconductor 功能描述:PQ38K 8544 - Bulk |
| MPC8544AVTARJ | 功能描述:微處理器 - MPU PQ3 8544 COMMERCIAL RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8544AVTARJA | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC PQ38K 8544 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8544COMEDEV | 功能描述:開發(fā)板和工具包 - 其他處理器 EXPRESS KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8544CVTALF | 功能描述:微處理器 - MPU PQ38K 8544 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。