參數(shù)資料
型號: MPC8541ECPXALF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 80/88頁
文件大?。?/td> 1110K
代理商: MPC8541ECPXALF
MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
81
System Design Information
17.8.1 Termination of Unused Signals
If the JTAG interface and COP header are not used, Freescale recommends the following connections:
TRST should be tied to HRESET through a 0 k
Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in Figure 52. If this is not possible, the isolation resistor allows future access to TRST in
case a JTAG interface may need to be wired onto the system in future debug situations.
Tie TCK to OVDD through a 10 kΩ resistor. This prevents TCK from changing state and reading
incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
相關(guān)PDF資料
PDF描述
MPC8541VTALE 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
MPC8541VTAKF 32-BIT, 600 MHz, RISC PROCESSOR, PBGA783
MPC8541PXALE 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
MPC8541PXAPF 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
MPC8541VTAQE 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
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