參數(shù)資料
型號(hào): MPC8540PXAPDB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 833 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 24/104頁
文件大小: 2133K
代理商: MPC8540PXAPDB
MPC8540 Integrated Processor Hardware Specifications, Rev. 3.1
26
Freescale Semiconductor
Ethernet: Three-Speed,10/100, MII Management
Figure 8 provides the AC test load for TSEC.
Figure 8. TSEC AC Test Load
Figure 9 shows the GMII receive AC timing diagram.
Figure 9. GMII Receive AC Timing Diagram
8.2.2 MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
RX_CLK clock fall time (80%-20%)
tGRXF
2
1.0
ns
Note:
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state
(V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII
receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock
reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation
is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX
represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2.Guaranteed by design.
Table 23. GMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Output
LVDD/2
RL = 50
Z0 = 50
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
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