參數(shù)資料
型號(hào)： MPC8540CVT667JC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 92/104頁(yè)
文件大小： 0K
描述： MPU POWERQUICC III 783FCPBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC85xx
處理器類(lèi)型： 32-位 MPC85xx PowerQUICC III
速度： 667MHz
電壓： 1.2V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
MPC8540 Integrated Processor Hardware Specifications, Rev. 4.1
88
Freescale Semiconductor
System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8540.
17.1 System Clocking
The MPC8540includes two PLLs.
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 15.2, “Platform/System PLL Ratio.”
2. The e500 Core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in Section 15.3, “e500 Core PLL Ratio.”
17.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1 and
AVDD2, respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages
will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide three independent filter circuits as illustrated in Figure 52, one to each of the three AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
Figure 52 shows the PLL power supply filter circuit.
Figure 52. PLL Power Supply Filter Circuit
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
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MPC8540PX667LB 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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MPC8540PX833LB 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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