參數(shù)資料
型號: MPC8536EBVTAVLA
廠商: Freescale Semiconductor
文件頁數(shù): 41/126頁
文件大?。?/td> 0K
描述: MPU PWRQUICC III 1500MHZ 783PBGA
產(chǎn)品培訓(xùn)模塊: MPC8536E QUICC III Processor
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8536EBVTAVL
MPC8536EBVTAVL-ND
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
21
2
Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
This table provides the absolute maximum ratings.
25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No
Connect” or terminated through 2–10 K
Ω pull-up resistors with the default of internal arbiter if the address pins are not
connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
26. When operating in DDR2 mode, connect MDIC[0] to ground through an 18.2-
Ω (full-strength mode) or 36.4-Ω (half-strength
mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 18.2-
Ω (full-strength mode) or 36.4-Ω (half-strength
mode) precision 1% resistor. When operating in DDR3 mode, connect MDIC[0] to ground through an 20-
Ω (full-strength
mode) or 40-
Ω (half-strength mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 20-Ω (full-strength
mode) or 40-
Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR IOs.
27. Connect to GND through a pull down 1 k
Ω resistor
28. It must be the same as VDD_CORE
29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when
GCR[DEEPSLEEP_Z] =1.
30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is
configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is
recommended to tie it off to GND when DDR controller is running in synchronous mode. See the
MPC8536E PowerQUICC
III Integrated Host Processor Family Reference Manual, Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”, section 4.4.3.2
“DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding DDR controller
operation in asynchronous and synchronous modes.
31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and
RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.
32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for
SD/MMC card specification.
33. For systems that boot from Local Bus(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is
required.
Table 2. Absolute Maximum Ratings1
Characteristic
Symbol
Max Value
Unit Notes
Core supply voltage
VDD_CORE
–0.3 to 1.21
V
Platform supply voltage
VDD_PLAT
–0.3 to 1.1
V
PLL core supply voltage
AVDD_CORE
–0.3 to 1.21
V
PLL other supply voltage
AVDD
–0.3 to 1.1
V
Core power supply for SerDes transceivers
SVDD, S2VDD
–0.3 to 1.1
V
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
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