參數(shù)資料
型號(hào): MPC8536CVTAVLA
廠商: Freescale Semiconductor
文件頁數(shù): 15/126頁
文件大?。?/td> 0K
描述: MPU PWRQUICC III 1500MHZ 783PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8536CVTAVL
MPC8536CVTAVL-ND
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
111
2.24.1
Thermal Characteristics
This table provides the package thermal characteristics.
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material
was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the chip’s thermal
model without a lid is shown in Figure 72 The substrate is modeled as a block 29 x 29 x 1.2 mm with an in-plane conductivity
of 19.8 W/mK and a through-plane conductivity of 1.13 W/mK. The solder balls and air are modeled as a single block
29 x 29 x 0.5 mm with an in-plane conductivity of 0.034 W/mK and a through plane conductivity of 12.1 W/mK. The die is
modeled as 9.6 x 9.57 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal resistance
between the die and substrate assuming a conductivity of 7.5 W/mK in the thickness dimension of 0.07 mm. The die is centered
on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual
dimensions.
2.24.2
Recommended Thermal Model
This table shows the chip’s thermal model.
Table 79. Package Thermal Characteristics
Characteristic
JEDEC Board
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection
Single layer board (1s)
RθJA
23
°C/W
1, 2
Junction-to-ambient Natural Convection
Four layer board (2s2p)
RθJA
18
°C/W
1, 2
Junction-to-ambient (@200 ft/min)
Single layer board (1s)
RθJA
18
°C/W
1, 2
Junction-to-ambient (@200 ft/min)
Four layer board (2s2p)
RθJA
14
°C/W
1, 2
Junction-to-board thermal
RθJB
10
°C/W
3
Junction-to-case thermal
RθJC
< 0.1
°C/W
4
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method
(MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 C/W
C/W
Table 80. Thermal Model
Conductivity
Value
Units
Die (9.6x9.6
× 0.85 mm)
Silicon
Temperature dependent
Bump/Underfill (9.6 x 9.6
× 0.07 mm) Collapsed Thermal Resistance
Kz
7.5
W/mK
Substrate (29
× 29 × 1.2 mm)
Kx
19.8
W/mK
Ky
19.8
Kz
1.13
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