參數(shù)資料
型號： MPC8536CVTAVLA
廠商： Freescale Semiconductor
文件頁數(shù)： 121/126頁
文件大小： 0K
描述： MPU PWRQUICC III 1500MHZ 783PBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
其它名稱： MPC8536CVTAVL
MPC8536CVTAVL-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
94
2.20.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the chip’s SerDes reference clock inputs is different depending on the signaling mode used to
connect the clock driver chip and SerDes reference clock inputs as described below.
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or
between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
—For external DC-coupled connection, as described in Section 2.20.2.1, “SerDes Reference Clock Receiver
Characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) to be between 100 mV and 400 mV. Figure 59 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
—For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SnGND. Each signal wire of the differential inputs is allowed to swing below and
above the command mode voltage (SnGND). Figure 60 shows the SerDes reference clock input requirement for
AC-coupled connection scheme.
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be
between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or
tied to ground.
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 61 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled)
SD
n_REF_CLK
SD
n_REF_CLK
Vmax < 800 mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
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