參數(shù)資料
型號： MPC8536BVTAVLA
廠商： Freescale Semiconductor
文件頁數(shù)： 122/126頁
文件大?。?/td> 0K
描述： MPU PWRQUICC III 1500MHZ 783PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
其它名稱： MPC8536BVTAVL
MPC8536BVTAVL-ND
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
95
Figure 60. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 61. Single-Ended Reference Clock Input DC Requirements
2.20.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to SnGND (xcorevss), the differential reference clocks inputs are HCSL (High-Speed Current
Steering Logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to
be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection.
LVPECL (Low Voltage Positive Emitter-Coupled Logic) outputs can produce signal with too large amplitude and may need to
be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
NOTE
Figure 62 to Figure 65 below are for conceptual reference only. Due to the fact that clock
driver chip's internal structure, output impedance and termination requirements are
different between various clock driver chip manufacturers, it is very possible that the clock
circuit reference designs provided by clock driver chip vendor are different from what is
shown below. They might also vary from one vendor to the other. Therefore, Freescale
Semiconductor can neither provide the optimal clock driver reference circuits, nor
guarantee the correctness of the following clock driver connection reference circuits. The
system designer is recommended to contact the selected clock driver chip vendor for the
optimal reference circuits with the chip’s SerDes reference clock receiver requirement
provided in this document.
SD
n_REF_CLK
SD
n_REF_CLK
Vcm
200mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD
n_REF_CLK
SD
n_REF_CLK
400 mV < SD
n_REF_CLK Input Amplitude < 800 mV
0V
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