參數(shù)資料
型號: MPC8535CVTATH
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1250 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù): 97/126頁
文件大小: 2861K
代理商: MPC8535CVTATH
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
enhanced Local Bus Controller (eLBC)
Freescale Semiconductor
72
Local bus clock to data valid for LAD/LDP
tLBKLOV2
—0.5
ns
4
Local bus clock to address valid for LAD, and LALE
tLBKLOV3
—0.5
ns
4
Local bus clock to LALE assertion
tLBKLOV4
—0.5
ns
4
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKLOX1
2.2
ns
4,8
Output hold from local bus clock for LAD/LDP
tLBKLOX2
2.2
ns
4,8
Local bus clock to output high Impedance (except LAD/LDP and LALE)
tLBKLOZ1
—0.1
ns
7
Local bus clock to output high impedance for LAD/LDP
tLBKLOZ2
—0.1
ns
7
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
with LBCR[AHD] = 0.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
8. These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing
parameters.
Table 54. Local Bus General Timing Parameters—PLL Bypassed (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
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