參數(shù)資料
型號： MPC8535AVTANG
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù)： 73/126頁
文件大小： 2861K
代理商： MPC8535AVTANG
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Freescale Semiconductor
50
A timing diagram for TBI receive appears in Figure 24.
.
Figure 24. TBI Single-Clock Mode Receive AC Timing Diagram
2.9.2.6
RGMII and RTBI AC Timing Specifications
Table 35 presents the RGMII and RTBI AC timing specifications.
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with L/TVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT_TX
–500
0
500
ps
Data to clock input skew (at receiver) 2
tSKRGT_RX
1.0
—
2.8
ns
Clock period duration 3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000BASE-T4
tRGTH/tRGT
45
—
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3, 4
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
0.75
ns
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to
represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note
also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than
1.5 ns will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transition to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
tTRR
tTRRH
tTRRF
tTRRR
RX_CLK
RCG[9:0]
valid data
tTRRDX
tTRRDV
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